JPS54100221A - Video signal process circuit - Google Patents

Video signal process circuit

Info

Publication number
JPS54100221A
JPS54100221A JP620278A JP620278A JPS54100221A JP S54100221 A JPS54100221 A JP S54100221A JP 620278 A JP620278 A JP 620278A JP 620278 A JP620278 A JP 620278A JP S54100221 A JPS54100221 A JP S54100221A
Authority
JP
Japan
Prior art keywords
signal
circuit
added
video signal
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP620278A
Other languages
Japanese (ja)
Other versions
JPS6216065B2 (en
Inventor
Hidekazu Funashiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP620278A priority Critical patent/JPS54100221A/en
Publication of JPS54100221A publication Critical patent/JPS54100221A/en
Publication of JPS6216065B2 publication Critical patent/JPS6216065B2/ja
Granted legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE: To obtain a high-contrast picture by processing the signal through the secondary differential circuit and the waveform shaping circuit through which the noise is suppressed with the low frequency to reduce the overshoot and the contour is emphasized.
CONSTITUTION: The video signal process circuit suppresses the noise of the video signal for the TV receiver, the VTR and the like. In this process circuit, the video signal of input terminal 1 is isolated into the primary differential HPF2 and LPF3 to be supplied, and the signals passed through HPF2 are made to pass through expansion circuit 4 to be turned to signal C with the noise deleted and then added to output signal 6 of LPF2 via adder circuit 5 to deliver signal d. Signal d is furthermore isolated into secondary HPF7 and LPF8 to be added, and the signals passed through HPF7 are added to polarity reversing circuit 9 to deliver signal e to the output. Then signal e is added to the signal passed through LPF8 through adder circuit 10. Thus, output signal f featuring reduced overshoot is delivered to output terminal 6.
COPYRIGHT: (C)1979,JPO&Japio
JP620278A 1978-01-25 1978-01-25 Video signal process circuit Granted JPS54100221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP620278A JPS54100221A (en) 1978-01-25 1978-01-25 Video signal process circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP620278A JPS54100221A (en) 1978-01-25 1978-01-25 Video signal process circuit

Publications (2)

Publication Number Publication Date
JPS54100221A true JPS54100221A (en) 1979-08-07
JPS6216065B2 JPS6216065B2 (en) 1987-04-10

Family

ID=11631945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP620278A Granted JPS54100221A (en) 1978-01-25 1978-01-25 Video signal process circuit

Country Status (1)

Country Link
JP (1) JPS54100221A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4969012A (en) * 1972-11-07 1974-07-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4969012A (en) * 1972-11-07 1974-07-04

Also Published As

Publication number Publication date
JPS6216065B2 (en) 1987-04-10

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