JPS5396969U - - Google Patents

Info

Publication number
JPS5396969U
JPS5396969U JP179678U JP179678U JPS5396969U JP S5396969 U JPS5396969 U JP S5396969U JP 179678 U JP179678 U JP 179678U JP 179678 U JP179678 U JP 179678U JP S5396969 U JPS5396969 U JP S5396969U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP179678U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP179678U priority Critical patent/JPS5396969U/ja
Publication of JPS5396969U publication Critical patent/JPS5396969U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
JP179678U 1978-01-10 1978-01-10 Pending JPS5396969U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP179678U JPS5396969U (en) 1978-01-10 1978-01-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP179678U JPS5396969U (en) 1978-01-10 1978-01-10

Publications (1)

Publication Number Publication Date
JPS5396969U true JPS5396969U (en) 1978-08-07

Family

ID=28688839

Family Applications (1)

Application Number Title Priority Date Filing Date
JP179678U Pending JPS5396969U (en) 1978-01-10 1978-01-10

Country Status (1)

Country Link
JP (1) JPS5396969U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435744U (en) * 1987-08-28 1989-03-03

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3474297A (en) * 1967-06-30 1969-10-21 Texas Instruments Inc Interconnection system for complex semiconductor arrays

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3474297A (en) * 1967-06-30 1969-10-21 Texas Instruments Inc Interconnection system for complex semiconductor arrays

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6435744U (en) * 1987-08-28 1989-03-03

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