JPS5391560A - Logic circuit system - Google Patents

Logic circuit system

Info

Publication number
JPS5391560A
JPS5391560A JP11159677A JP11159677A JPS5391560A JP S5391560 A JPS5391560 A JP S5391560A JP 11159677 A JP11159677 A JP 11159677A JP 11159677 A JP11159677 A JP 11159677A JP S5391560 A JPS5391560 A JP S5391560A
Authority
JP
Japan
Prior art keywords
logic circuit
circuit system
rom
igfet
eliminating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11159677A
Other languages
Japanese (ja)
Other versions
JPS5619134B2 (en
Inventor
Masataka Hirasawa
Kenji Kawatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11159677A priority Critical patent/JPS5391560A/en
Publication of JPS5391560A publication Critical patent/JPS5391560A/en
Publication of JPS5619134B2 publication Critical patent/JPS5619134B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Read Only Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent the number of elements from increasing in ROM by eliminating the need for clock pulses whose pulse widths are different at every stage for the integrated-circuit implementation of ROM using IGFET.
JP11159677A 1977-09-19 1977-09-19 Logic circuit system Granted JPS5391560A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11159677A JPS5391560A (en) 1977-09-19 1977-09-19 Logic circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11159677A JPS5391560A (en) 1977-09-19 1977-09-19 Logic circuit system

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3869872A Division JPS52663B2 (en) 1972-04-19 1972-04-19

Publications (2)

Publication Number Publication Date
JPS5391560A true JPS5391560A (en) 1978-08-11
JPS5619134B2 JPS5619134B2 (en) 1981-05-06

Family

ID=14565357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11159677A Granted JPS5391560A (en) 1977-09-19 1977-09-19 Logic circuit system

Country Status (1)

Country Link
JP (1) JPS5391560A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4389705A (en) * 1981-08-21 1983-06-21 Mostek Corporation Semiconductor memory circuit with depletion data transfer transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4389705A (en) * 1981-08-21 1983-06-21 Mostek Corporation Semiconductor memory circuit with depletion data transfer transistor

Also Published As

Publication number Publication date
JPS5619134B2 (en) 1981-05-06

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