JPS5379310A - Synchronous circuit - Google Patents

Synchronous circuit

Info

Publication number
JPS5379310A
JPS5379310A JP15573276A JP15573276A JPS5379310A JP S5379310 A JPS5379310 A JP S5379310A JP 15573276 A JP15573276 A JP 15573276A JP 15573276 A JP15573276 A JP 15573276A JP S5379310 A JPS5379310 A JP S5379310A
Authority
JP
Japan
Prior art keywords
synchronous circuit
synchronous
circuit
increasing
accurate period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15573276A
Other languages
Japanese (ja)
Other versions
JPS6036668B2 (en
Inventor
Kazuhiro Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP51155732A priority Critical patent/JPS6036668B2/en
Publication of JPS5379310A publication Critical patent/JPS5379310A/en
Publication of JPS6036668B2 publication Critical patent/JPS6036668B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain a more accurate period by increasing the number of polyphase clocks.
JP51155732A 1976-12-23 1976-12-23 synchronous circuit Expired JPS6036668B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51155732A JPS6036668B2 (en) 1976-12-23 1976-12-23 synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51155732A JPS6036668B2 (en) 1976-12-23 1976-12-23 synchronous circuit

Publications (2)

Publication Number Publication Date
JPS5379310A true JPS5379310A (en) 1978-07-13
JPS6036668B2 JPS6036668B2 (en) 1985-08-21

Family

ID=15612232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51155732A Expired JPS6036668B2 (en) 1976-12-23 1976-12-23 synchronous circuit

Country Status (1)

Country Link
JP (1) JPS6036668B2 (en)

Also Published As

Publication number Publication date
JPS6036668B2 (en) 1985-08-21

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