JPS5369511A - Frame multiplying system on pcm data transmission - Google Patents

Frame multiplying system on pcm data transmission

Info

Publication number
JPS5369511A
JPS5369511A JP14526376A JP14526376A JPS5369511A JP S5369511 A JPS5369511 A JP S5369511A JP 14526376 A JP14526376 A JP 14526376A JP 14526376 A JP14526376 A JP 14526376A JP S5369511 A JPS5369511 A JP S5369511A
Authority
JP
Japan
Prior art keywords
data transmission
pcm data
multiplying system
frame
frame multiplying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14526376A
Other languages
Japanese (ja)
Inventor
Kazuhisa Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14526376A priority Critical patent/JPS5369511A/en
Publication of JPS5369511A publication Critical patent/JPS5369511A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1629—Format building algorithm

Abstract

PURPOSE:To achieve the simplification of hardware and the improved efficiency of data multiplication by making the number of data bits, assigned to one multichannel, divisible by an integer and the entire data bits.
JP14526376A 1976-12-03 1976-12-03 Frame multiplying system on pcm data transmission Pending JPS5369511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14526376A JPS5369511A (en) 1976-12-03 1976-12-03 Frame multiplying system on pcm data transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14526376A JPS5369511A (en) 1976-12-03 1976-12-03 Frame multiplying system on pcm data transmission

Publications (1)

Publication Number Publication Date
JPS5369511A true JPS5369511A (en) 1978-06-21

Family

ID=15381074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14526376A Pending JPS5369511A (en) 1976-12-03 1976-12-03 Frame multiplying system on pcm data transmission

Country Status (1)

Country Link
JP (1) JPS5369511A (en)

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