JPS5369503A - Receiving circuit for dial pulses - Google Patents

Receiving circuit for dial pulses

Info

Publication number
JPS5369503A
JPS5369503A JP14538576A JP14538576A JPS5369503A JP S5369503 A JPS5369503 A JP S5369503A JP 14538576 A JP14538576 A JP 14538576A JP 14538576 A JP14538576 A JP 14538576A JP S5369503 A JPS5369503 A JP S5369503A
Authority
JP
Japan
Prior art keywords
receiving circuit
dial pulses
dial
pulses
varistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14538576A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5551397B2 (cs
Inventor
Shozo Nishimura
Hidemi Harada
Moriyoshi Ishida
Kenichi Hanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP14538576A priority Critical patent/JPS5369503A/ja
Publication of JPS5369503A publication Critical patent/JPS5369503A/ja
Publication of JPS5551397B2 publication Critical patent/JPS5551397B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q1/00Details of selecting apparatus or arrangements
    • H04Q1/18Electrical details
    • H04Q1/30Signalling arrangements; Manipulation of signalling currents
    • H04Q1/32Signalling arrangements; Manipulation of signalling currents using trains of DC pulses
    • H04Q1/36Pulse-correcting arrangements, e.g. for reducing effects due to interference

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
JP14538576A 1976-12-02 1976-12-02 Receiving circuit for dial pulses Granted JPS5369503A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14538576A JPS5369503A (en) 1976-12-02 1976-12-02 Receiving circuit for dial pulses

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14538576A JPS5369503A (en) 1976-12-02 1976-12-02 Receiving circuit for dial pulses

Publications (2)

Publication Number Publication Date
JPS5369503A true JPS5369503A (en) 1978-06-21
JPS5551397B2 JPS5551397B2 (cs) 1980-12-24

Family

ID=15384011

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14538576A Granted JPS5369503A (en) 1976-12-02 1976-12-02 Receiving circuit for dial pulses

Country Status (1)

Country Link
JP (1) JPS5369503A (cs)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56121385U (cs) * 1980-02-16 1981-09-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56121385U (cs) * 1980-02-16 1981-09-16

Also Published As

Publication number Publication date
JPS5551397B2 (cs) 1980-12-24

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