JPS5363960A - Degital phase restriction loop circuit - Google Patents

Degital phase restriction loop circuit

Info

Publication number
JPS5363960A
JPS5363960A JP13926576A JP13926576A JPS5363960A JP S5363960 A JPS5363960 A JP S5363960A JP 13926576 A JP13926576 A JP 13926576A JP 13926576 A JP13926576 A JP 13926576A JP S5363960 A JPS5363960 A JP S5363960A
Authority
JP
Japan
Prior art keywords
degital
loop circuit
phase restriction
restriction loop
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13926576A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5724700B2 (enExample
Inventor
Tadahiro Wada
Keiichi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13926576A priority Critical patent/JPS5363960A/ja
Publication of JPS5363960A publication Critical patent/JPS5363960A/ja
Publication of JPS5724700B2 publication Critical patent/JPS5724700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
JP13926576A 1976-11-19 1976-11-19 Degital phase restriction loop circuit Granted JPS5363960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13926576A JPS5363960A (en) 1976-11-19 1976-11-19 Degital phase restriction loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13926576A JPS5363960A (en) 1976-11-19 1976-11-19 Degital phase restriction loop circuit

Publications (2)

Publication Number Publication Date
JPS5363960A true JPS5363960A (en) 1978-06-07
JPS5724700B2 JPS5724700B2 (enExample) 1982-05-25

Family

ID=15241248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13926576A Granted JPS5363960A (en) 1976-11-19 1976-11-19 Degital phase restriction loop circuit

Country Status (1)

Country Link
JP (1) JPS5363960A (enExample)

Also Published As

Publication number Publication date
JPS5724700B2 (enExample) 1982-05-25

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