JPS5360107A - Frequency catching circuit - Google Patents

Frequency catching circuit

Info

Publication number
JPS5360107A
JPS5360107A JP13567976A JP13567976A JPS5360107A JP S5360107 A JPS5360107 A JP S5360107A JP 13567976 A JP13567976 A JP 13567976A JP 13567976 A JP13567976 A JP 13567976A JP S5360107 A JPS5360107 A JP S5360107A
Authority
JP
Japan
Prior art keywords
frequency
catching circuit
frequency catching
circuit
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13567976A
Other languages
Japanese (ja)
Inventor
Yoshio Matsuo
Junji Namiki
Yukitsuna Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13567976A priority Critical patent/JPS5360107A/en
Priority to US05/849,581 priority patent/US4168398A/en
Publication of JPS5360107A publication Critical patent/JPS5360107A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE:To secure a presumption for the frequency covered with noise and interference wave as well as the frequency of the signal whose level is indefinite, by restricting the frequency of the voltage control oscillator when a level detector has the maximum level output.
JP13567976A 1976-11-10 1976-11-10 Frequency catching circuit Pending JPS5360107A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP13567976A JPS5360107A (en) 1976-11-10 1976-11-10 Frequency catching circuit
US05/849,581 US4168398A (en) 1976-11-10 1977-11-08 Initial acquisition signal detection system for TDMA satellite communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13567976A JPS5360107A (en) 1976-11-10 1976-11-10 Frequency catching circuit

Publications (1)

Publication Number Publication Date
JPS5360107A true JPS5360107A (en) 1978-05-30

Family

ID=15157382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13567976A Pending JPS5360107A (en) 1976-11-10 1976-11-10 Frequency catching circuit

Country Status (1)

Country Link
JP (1) JPS5360107A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4860511A (en) * 1971-11-29 1973-08-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4860511A (en) * 1971-11-29 1973-08-24

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