JPS5339835A - Method of designating address - Google Patents

Method of designating address

Info

Publication number
JPS5339835A
JPS5339835A JP11452177A JP11452177A JPS5339835A JP S5339835 A JPS5339835 A JP S5339835A JP 11452177 A JP11452177 A JP 11452177A JP 11452177 A JP11452177 A JP 11452177A JP S5339835 A JPS5339835 A JP S5339835A
Authority
JP
Japan
Prior art keywords
designating address
designating
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11452177A
Other languages
English (en)
Other versions
JPS5834038B2 (ja
Inventor
Ii Sukuribaa Robaato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5339835A publication Critical patent/JPS5339835A/ja
Publication of JPS5834038B2 publication Critical patent/JPS5834038B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP52114521A 1976-09-22 1977-09-22 アドレス指定方法 Expired JPS5834038B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/726,019 US4092715A (en) 1976-09-22 1976-09-22 Input-output unit having extended addressing capability

Publications (2)

Publication Number Publication Date
JPS5339835A true JPS5339835A (en) 1978-04-12
JPS5834038B2 JPS5834038B2 (ja) 1983-07-23

Family

ID=24916886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52114521A Expired JPS5834038B2 (ja) 1976-09-22 1977-09-22 アドレス指定方法

Country Status (4)

Country Link
US (1) US4092715A (ja)
JP (1) JPS5834038B2 (ja)
AU (1) AU2877477A (ja)
GB (1) GB1593312A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01131000A (ja) * 1987-11-17 1989-05-23 Hidetoshi Miyakoshi 七宝風装飾板の製造方法

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400729A1 (fr) * 1977-08-17 1979-03-16 Cii Honeywell Bull Dispositif pour la transformation d'adresses virtuelles en adresses physiques dans un systeme de traitement de donnees
US4363091A (en) * 1978-01-31 1982-12-07 Intel Corporation Extended address, single and multiple bit microprocessor
FR2430041A1 (fr) * 1978-06-28 1980-01-25 Fujitsu Ltd Dispositif de traduction dynamique d'adresse
JPS6013501B2 (ja) * 1978-09-18 1985-04-08 富士通株式会社 仮想計算機システムにおけるチヤネルアドレス制御方式
US4251860A (en) * 1978-10-23 1981-02-17 International Business Machines Corporation Virtual addressing apparatus employing separate data paths for segment and offset portions of a virtual address and utilizing only the offset portion to calculate virtual address
US4231088A (en) * 1978-10-23 1980-10-28 International Business Machines Corporation Allocating and resolving next virtual pages for input/output
US4300193A (en) * 1979-01-31 1981-11-10 Honeywell Information Systems Inc. Data processing system having data multiplex control apparatus
US4334287A (en) * 1979-04-12 1982-06-08 Sperry Rand Corporation Buffer memory arrangement
US4315310A (en) * 1979-09-28 1982-02-09 Intel Corporation Input/output data processing system
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
US4419728A (en) * 1981-06-22 1983-12-06 Bell Telephone Laboratories, Incorporated Channel interface circuit providing virtual channel number translation and direct memory access
WO1983000576A1 (en) * 1981-08-12 1983-02-17 Eggebrecht, Lewis, Clark Extended addressing apparatus and method for direct storage access devices
US4464713A (en) * 1981-08-17 1984-08-07 International Business Machines Corporation Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store
AU555632B2 (en) * 1982-03-12 1986-10-02 Honeywell Information Systems Incorp. Multiplexing central to peripheral control signals
JPS58225422A (ja) * 1982-06-25 1983-12-27 Toshiba Corp デ−タ制御装置
US4550368A (en) * 1982-07-02 1985-10-29 Sun Microsystems, Inc. High-speed memory and memory management system
IN165278B (ja) * 1984-09-21 1989-09-09 Digital Equipment Corp
US4796177A (en) * 1985-04-30 1989-01-03 Fujitsu Limited Address extension system
IT1183808B (it) * 1985-04-30 1987-10-22 Olivetti & Co Spa Circuito elettronico per collegare un microprocessore ad una memoria ad elevata capacita
US4972338A (en) * 1985-06-13 1990-11-20 Intel Corporation Memory management for microprocessor system
US4858117A (en) * 1987-08-07 1989-08-15 Bull Hn Information Systems Inc. Apparatus and method for preventing computer access by unauthorized personnel
JP2507756B2 (ja) * 1987-10-05 1996-06-19 株式会社日立製作所 情報処理装置
US4965720A (en) * 1988-07-18 1990-10-23 International Business Machines Corporation Directed address generation for virtual-address data processors
US5469556A (en) * 1989-12-12 1995-11-21 Harris Corporation Resource access security system for controlling access to resources of a data processing system
JP3517417B2 (ja) * 1992-01-28 2004-04-12 株式会社日立製作所 データ転送装置
US5805930A (en) * 1995-05-15 1998-09-08 Nvidia Corporation System for FIFO informing the availability of stages to store commands which include data and virtual address sent directly from application programs
FR2749681B1 (fr) * 1996-06-10 1998-07-10 Bull Sa Circuit pour transborder des donnees entre memoires distantes et calculateur comprenant un tel circuit
US5987582A (en) * 1996-09-30 1999-11-16 Cirrus Logic, Inc. Method of obtaining a buffer contiguous memory and building a page table that is accessible by a peripheral graphics device
US6684305B1 (en) 2001-04-24 2004-01-27 Advanced Micro Devices, Inc. Multiprocessor system implementing virtual memory using a shared memory, and a page replacement method for maintaining paged memory coherence
CN117375625B (zh) * 2023-12-04 2024-03-22 深流微智能科技(深圳)有限公司 地址空间的动态解压缩方法、地址解压器、设备及介质

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576543A (en) * 1967-05-03 1971-04-27 English Electric Computers Ltd Data handling arrangements
US3704453A (en) * 1971-02-23 1972-11-28 Ibm Catenated files
FR122199A (ja) * 1973-12-17
US3947823A (en) * 1973-12-26 1976-03-30 International Business Machines Corp. Means for coordinating asynchronous main store accesses in a multiprocessing system using virtual storage
US3955180A (en) * 1974-01-02 1976-05-04 Honeywell Information Systems Inc. Table driven emulation system
FR119649A (ja) * 1975-03-24
US3976978A (en) * 1975-03-26 1976-08-24 Honeywell Information Systems, Inc. Method of generating addresses to a paged memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01131000A (ja) * 1987-11-17 1989-05-23 Hidetoshi Miyakoshi 七宝風装飾板の製造方法

Also Published As

Publication number Publication date
US4092715A (en) 1978-05-30
JPS5834038B2 (ja) 1983-07-23
AU2877477A (en) 1979-03-22
GB1593312A (en) 1981-07-15

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