JPS5335411Y2 - - Google Patents
Info
- Publication number
- JPS5335411Y2 JPS5335411Y2 JP6131374U JP6131374U JPS5335411Y2 JP S5335411 Y2 JPS5335411 Y2 JP S5335411Y2 JP 6131374 U JP6131374 U JP 6131374U JP 6131374 U JP6131374 U JP 6131374U JP S5335411 Y2 JPS5335411 Y2 JP S5335411Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6131374U JPS5335411Y2 (ja) | 1974-05-30 | 1974-05-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6131374U JPS5335411Y2 (ja) | 1974-05-30 | 1974-05-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS50150269U JPS50150269U (ja) | 1975-12-13 |
JPS5335411Y2 true JPS5335411Y2 (ja) | 1978-08-30 |
Family
ID=28221740
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6131374U Expired JPS5335411Y2 (ja) | 1974-05-30 | 1974-05-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5335411Y2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5939915B2 (ja) * | 1976-12-13 | 1984-09-27 | 富士通株式会社 | 半導体レ−ザの出力光の波長安定化方式 |
-
1974
- 1974-05-30 JP JP6131374U patent/JPS5335411Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS50150269U (ja) | 1975-12-13 |