JPS53128951A - Arithmetic logic device - Google Patents
Arithmetic logic deviceInfo
- Publication number
- JPS53128951A JPS53128951A JP4354177A JP4354177A JPS53128951A JP S53128951 A JPS53128951 A JP S53128951A JP 4354177 A JP4354177 A JP 4354177A JP 4354177 A JP4354177 A JP 4354177A JP S53128951 A JPS53128951 A JP S53128951A
- Authority
- JP
- Japan
- Prior art keywords
- logic device
- arithmetic logic
- register
- bit number
- secure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
Abstract
PURPOSE:To secure a high speed execution of the operation to obtain the bit number of ''1'' or ''0'', by adding a means to obtain the bit number of register 1 at one side as well as adding a means to give addition through the binary notation to the other register for the arithmetic logic device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4354177A JPS53128951A (en) | 1977-04-18 | 1977-04-18 | Arithmetic logic device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4354177A JPS53128951A (en) | 1977-04-18 | 1977-04-18 | Arithmetic logic device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS53128951A true JPS53128951A (en) | 1978-11-10 |
Family
ID=12666590
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4354177A Pending JPS53128951A (en) | 1977-04-18 | 1977-04-18 | Arithmetic logic device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS53128951A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0126247A2 (en) * | 1983-05-18 | 1984-11-28 | International Business Machines Corporation | Computer system |
-
1977
- 1977-04-18 JP JP4354177A patent/JPS53128951A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0126247A2 (en) * | 1983-05-18 | 1984-11-28 | International Business Machines Corporation | Computer system |
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