JPS53124037A - Multiple memory control device - Google Patents

Multiple memory control device

Info

Publication number
JPS53124037A
JPS53124037A JP3856877A JP3856877A JPS53124037A JP S53124037 A JPS53124037 A JP S53124037A JP 3856877 A JP3856877 A JP 3856877A JP 3856877 A JP3856877 A JP 3856877A JP S53124037 A JPS53124037 A JP S53124037A
Authority
JP
Japan
Prior art keywords
control device
memory control
multiple memory
transfer
malfunction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3856877A
Other languages
Japanese (ja)
Inventor
Keikichi Tamaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3856877A priority Critical patent/JPS53124037A/en
Publication of JPS53124037A publication Critical patent/JPS53124037A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To avoid the malfunction by displaying that the information is under transfer between the memory planes and inhibiting the memory access action during the transfer time.
JP3856877A 1977-04-06 1977-04-06 Multiple memory control device Pending JPS53124037A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3856877A JPS53124037A (en) 1977-04-06 1977-04-06 Multiple memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3856877A JPS53124037A (en) 1977-04-06 1977-04-06 Multiple memory control device

Publications (1)

Publication Number Publication Date
JPS53124037A true JPS53124037A (en) 1978-10-30

Family

ID=12528894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3856877A Pending JPS53124037A (en) 1977-04-06 1977-04-06 Multiple memory control device

Country Status (1)

Country Link
JP (1) JPS53124037A (en)

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