JPS5277544A - Address transition control device - Google Patents
Address transition control deviceInfo
- Publication number
- JPS5277544A JPS5277544A JP50154311A JP15431175A JPS5277544A JP S5277544 A JPS5277544 A JP S5277544A JP 50154311 A JP50154311 A JP 50154311A JP 15431175 A JP15431175 A JP 15431175A JP S5277544 A JPS5277544 A JP S5277544A
- Authority
- JP
- Japan
- Prior art keywords
- control device
- transition control
- address transition
- transition buffer
- invalid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50154311A JPS5277544A (en) | 1975-12-23 | 1975-12-23 | Address transition control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50154311A JPS5277544A (en) | 1975-12-23 | 1975-12-23 | Address transition control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5277544A true JPS5277544A (en) | 1977-06-30 |
| JPS5414458B2 JPS5414458B2 (en:Method) | 1979-06-07 |
Family
ID=15581330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50154311A Granted JPS5277544A (en) | 1975-12-23 | 1975-12-23 | Address transition control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5277544A (en:Method) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148329A (en) * | 1978-05-15 | 1979-11-20 | Toshiba Corp | Buffer memory control system and information processor containing buffer memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4912144A (en:Method) * | 1972-05-10 | 1974-02-02 | ||
| JPS4936487A (en:Method) * | 1972-08-09 | 1974-04-04 | ||
| JPS4975037A (en:Method) * | 1972-10-17 | 1974-07-19 | ||
| JPS5082941A (en:Method) * | 1973-11-24 | 1975-07-04 |
-
1975
- 1975-12-23 JP JP50154311A patent/JPS5277544A/ja active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4912144A (en:Method) * | 1972-05-10 | 1974-02-02 | ||
| JPS4936487A (en:Method) * | 1972-08-09 | 1974-04-04 | ||
| JPS4975037A (en:Method) * | 1972-10-17 | 1974-07-19 | ||
| JPS5082941A (en:Method) * | 1973-11-24 | 1975-07-04 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54148329A (en) * | 1978-05-15 | 1979-11-20 | Toshiba Corp | Buffer memory control system and information processor containing buffer memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5414458B2 (en:Method) | 1979-06-07 |
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