JPS5239892Y2 - - Google Patents
Info
- Publication number
- JPS5239892Y2 JPS5239892Y2 JP8263972U JP8263972U JPS5239892Y2 JP S5239892 Y2 JPS5239892 Y2 JP S5239892Y2 JP 8263972 U JP8263972 U JP 8263972U JP 8263972 U JP8263972 U JP 8263972U JP S5239892 Y2 JPS5239892 Y2 JP S5239892Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Manufacturing Of Electrical Connectors (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8263972U JPS5239892Y2 (enrdf_load_html_response) | 1972-07-11 | 1972-07-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8263972U JPS5239892Y2 (enrdf_load_html_response) | 1972-07-11 | 1972-07-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4939985U JPS4939985U (enrdf_load_html_response) | 1974-04-08 |
| JPS5239892Y2 true JPS5239892Y2 (enrdf_load_html_response) | 1977-09-09 |
Family
ID=27990234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8263972U Expired JPS5239892Y2 (enrdf_load_html_response) | 1972-07-11 | 1972-07-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5239892Y2 (enrdf_load_html_response) |
-
1972
- 1972-07-11 JP JP8263972U patent/JPS5239892Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4939985U (enrdf_load_html_response) | 1974-04-08 |