JPS5239891Y2 - - Google Patents
Info
- Publication number
- JPS5239891Y2 JPS5239891Y2 JP1972111216U JP11121672U JPS5239891Y2 JP S5239891 Y2 JPS5239891 Y2 JP S5239891Y2 JP 1972111216 U JP1972111216 U JP 1972111216U JP 11121672 U JP11121672 U JP 11121672U JP S5239891 Y2 JPS5239891 Y2 JP S5239891Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1972111216U JPS5239891Y2 (pm) | 1972-09-25 | 1972-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1972111216U JPS5239891Y2 (pm) | 1972-09-25 | 1972-09-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4966361U JPS4966361U (pm) | 1974-06-10 |
| JPS5239891Y2 true JPS5239891Y2 (pm) | 1977-09-09 |
Family
ID=28335848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1972111216U Expired JPS5239891Y2 (pm) | 1972-09-25 | 1972-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5239891Y2 (pm) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4528096Y1 (pm) * | 1967-08-04 | 1970-10-29 |
-
1972
- 1972-09-25 JP JP1972111216U patent/JPS5239891Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4966361U (pm) | 1974-06-10 |