JPS5230814B1 - - Google Patents
Info
- Publication number
- JPS5230814B1 JPS5230814B1 JP50070235A JP7023575A JPS5230814B1 JP S5230814 B1 JPS5230814 B1 JP S5230814B1 JP 50070235 A JP50070235 A JP 50070235A JP 7023575 A JP7023575 A JP 7023575A JP S5230814 B1 JPS5230814 B1 JP S5230814B1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/525—Multiplying only in serial-serial fashion, i.e. both operands being entered serially
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Shift Register Type Memory (AREA)
- Complex Calculations (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81657369A | 1969-04-16 | 1969-04-16 | |
US2299170A | 1970-03-26 | 1970-03-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5230814B1 true JPS5230814B1 (ja) | 1977-08-10 |
Family
ID=26696595
Family Applications (6)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP45032633A Pending JPS5229133B1 (ja) | 1969-04-16 | 1970-04-16 | |
JP50070236A Pending JPS5230815B1 (ja) | 1969-04-16 | 1975-06-12 | |
JP50070237A Pending JPS5230816B1 (ja) | 1969-04-16 | 1975-06-12 | |
JP50070238A Pending JPS5230819B1 (ja) | 1969-04-16 | 1975-06-12 | |
JP50070235A Pending JPS5230814B1 (ja) | 1969-04-16 | 1975-06-12 | |
JP50070239A Pending JPS5234891B1 (ja) | 1969-04-16 | 1975-06-12 |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP45032633A Pending JPS5229133B1 (ja) | 1969-04-16 | 1970-04-16 | |
JP50070236A Pending JPS5230815B1 (ja) | 1969-04-16 | 1975-06-12 | |
JP50070237A Pending JPS5230816B1 (ja) | 1969-04-16 | 1975-06-12 | |
JP50070238A Pending JPS5230819B1 (ja) | 1969-04-16 | 1975-06-12 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50070239A Pending JPS5234891B1 (ja) | 1969-04-16 | 1975-06-12 |
Country Status (4)
Country | Link |
---|---|
US (1) | US3757231A (ja) |
JP (6) | JPS5229133B1 (ja) |
CA (1) | CA938730A (ja) |
GB (1) | GB1314841A (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3838345A (en) * | 1973-05-25 | 1974-09-24 | Sperry Rand Corp | Asynchronous shift cell |
US3976949A (en) * | 1975-01-13 | 1976-08-24 | Motorola, Inc. | Edge sensitive set-reset flip flop |
US3971960A (en) * | 1975-03-05 | 1976-07-27 | Motorola, Inc. | Flip-flop false output rejection circuit |
US4837740A (en) * | 1985-01-04 | 1989-06-06 | Sutherland Ivan F | Asynchronous first-in-first-out register structure |
US4679213A (en) * | 1985-01-08 | 1987-07-07 | Sutherland Ivan E | Asynchronous queue system |
US4814638A (en) * | 1987-06-08 | 1989-03-21 | Grumman Aerospace Corporation | High speed digital driver with selectable level shifter |
US5550780A (en) * | 1994-12-19 | 1996-08-27 | Cirrus Logic, Inc. | Two cycle asynchronous FIFO queue |
WO2008072173A2 (en) * | 2006-12-12 | 2008-06-19 | Nxp B.V. | Circuit with parallel functional circuits with multi-phase control inputs |
US10141930B2 (en) * | 2013-06-04 | 2018-11-27 | Nvidia Corporation | Three state latch |
CN109104180B (zh) * | 2018-08-08 | 2022-03-08 | 义乌工商职业技术学院 | 电子信息数据处理系统 |
CN110222001B (zh) * | 2019-05-20 | 2023-06-20 | 中国科学技术大学 | 基于PXIe机箱的反馈控制系统及反馈控制方法 |
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1970
- 1970-03-26 US US00022991A patent/US3757231A/en not_active Expired - Lifetime
- 1970-04-14 GB GB1780270A patent/GB1314841A/en not_active Expired
- 1970-04-16 JP JP45032633A patent/JPS5229133B1/ja active Pending
- 1970-04-16 CA CA080273A patent/CA938730A/en not_active Expired
-
1975
- 1975-06-12 JP JP50070236A patent/JPS5230815B1/ja active Pending
- 1975-06-12 JP JP50070237A patent/JPS5230816B1/ja active Pending
- 1975-06-12 JP JP50070238A patent/JPS5230819B1/ja active Pending
- 1975-06-12 JP JP50070235A patent/JPS5230814B1/ja active Pending
- 1975-06-12 JP JP50070239A patent/JPS5234891B1/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPS5234891B1 (ja) | 1977-09-06 |
CA938730A (en) | 1973-12-18 |
JPS5229133B1 (ja) | 1977-07-30 |
GB1314841A (en) | 1973-04-26 |
JPS5230819B1 (ja) | 1977-08-10 |
JPS5230816B1 (ja) | 1977-08-10 |
US3757231A (en) | 1973-09-04 |
JPS5230815B1 (ja) | 1977-08-10 |