JPS52155473U - - Google Patents
Info
- Publication number
- JPS52155473U JPS52155473U JP1976064474U JP6447476U JPS52155473U JP S52155473 U JPS52155473 U JP S52155473U JP 1976064474 U JP1976064474 U JP 1976064474U JP 6447476 U JP6447476 U JP 6447476U JP S52155473 U JPS52155473 U JP S52155473U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Junction Field-Effect Transistors (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976064474U JPS6120785Y2 (enExample) | 1976-05-20 | 1976-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1976064474U JPS6120785Y2 (enExample) | 1976-05-20 | 1976-05-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52155473U true JPS52155473U (enExample) | 1977-11-25 |
| JPS6120785Y2 JPS6120785Y2 (enExample) | 1986-06-21 |
Family
ID=28528639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1976064474U Expired JPS6120785Y2 (enExample) | 1976-05-20 | 1976-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6120785Y2 (enExample) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984583A (enExample) * | 1972-12-19 | 1974-08-14 |
-
1976
- 1976-05-20 JP JP1976064474U patent/JPS6120785Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4984583A (enExample) * | 1972-12-19 | 1974-08-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6120785Y2 (enExample) | 1986-06-21 |