JPS52130677U - - Google Patents

Info

Publication number
JPS52130677U
JPS52130677U JP3898776U JP3898776U JPS52130677U JP S52130677 U JPS52130677 U JP S52130677U JP 3898776 U JP3898776 U JP 3898776U JP 3898776 U JP3898776 U JP 3898776U JP S52130677 U JPS52130677 U JP S52130677U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3898776U
Other languages
Japanese (ja)
Other versions
JPS6116701Y2 (enrdf_load_stackoverflow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1976038987U priority Critical patent/JPS6116701Y2/ja
Priority to DE2714145A priority patent/DE2714145C2/de
Priority to CA275,206A priority patent/CA1079868A/en
Publication of JPS52130677U publication Critical patent/JPS52130677U/ja
Priority to US06/011,639 priority patent/US4283838A/en
Priority to CA344,749A priority patent/CA1108773A/en
Application granted granted Critical
Publication of JPS6116701Y2 publication Critical patent/JPS6116701Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1976038987U 1976-03-31 1976-03-31 Expired JPS6116701Y2 (enrdf_load_stackoverflow)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP1976038987U JPS6116701Y2 (enrdf_load_stackoverflow) 1976-03-31 1976-03-31
DE2714145A DE2714145C2 (de) 1976-03-31 1977-03-30 Gestanzte Metallträgerplatte für die Herstellung von kunststoffummantelten Halbleiterbauelementen
CA275,206A CA1079868A (en) 1976-03-31 1977-03-31 Plastic encapsulated semiconductor devices and method of making same
US06/011,639 US4283838A (en) 1976-03-31 1979-02-12 Method of making plastic encapsulated semiconductor devices
CA344,749A CA1108773A (en) 1976-03-31 1980-01-30 Plastic encapsulated semiconductor devices and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1976038987U JPS6116701Y2 (enrdf_load_stackoverflow) 1976-03-31 1976-03-31

Publications (2)

Publication Number Publication Date
JPS52130677U true JPS52130677U (enrdf_load_stackoverflow) 1977-10-04
JPS6116701Y2 JPS6116701Y2 (enrdf_load_stackoverflow) 1986-05-22

Family

ID=28498161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1976038987U Expired JPS6116701Y2 (enrdf_load_stackoverflow) 1976-03-31 1976-03-31

Country Status (1)

Country Link
JP (1) JPS6116701Y2 (enrdf_load_stackoverflow)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4988476A (enrdf_load_stackoverflow) * 1972-12-26 1974-08-23

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4988476A (enrdf_load_stackoverflow) * 1972-12-26 1974-08-23

Also Published As

Publication number Publication date
JPS6116701Y2 (enrdf_load_stackoverflow) 1986-05-22

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