JPS52114208A - Multiple digital suppressor - Google Patents

Multiple digital suppressor

Info

Publication number
JPS52114208A
JPS52114208A JP3108876A JP3108876A JPS52114208A JP S52114208 A JPS52114208 A JP S52114208A JP 3108876 A JP3108876 A JP 3108876A JP 3108876 A JP3108876 A JP 3108876A JP S52114208 A JPS52114208 A JP S52114208A
Authority
JP
Japan
Prior art keywords
circuit
suppressor
multiple digital
interruption duration
duration set
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3108876A
Other languages
Japanese (ja)
Inventor
Tomoji Morishita
Masahiro Sofue
Tsutomu Tateishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP3108876A priority Critical patent/JPS52114208A/en
Publication of JPS52114208A publication Critical patent/JPS52114208A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/20—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To make the circuit structure simpler by arranging an interruption duration set up circuit after comparing transmission/reception level and unifying a supression residual time set up circuit and an interruption duration set up circuit on a same constructure.
JP3108876A 1976-03-22 1976-03-22 Multiple digital suppressor Pending JPS52114208A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3108876A JPS52114208A (en) 1976-03-22 1976-03-22 Multiple digital suppressor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3108876A JPS52114208A (en) 1976-03-22 1976-03-22 Multiple digital suppressor

Publications (1)

Publication Number Publication Date
JPS52114208A true JPS52114208A (en) 1977-09-24

Family

ID=12321644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3108876A Pending JPS52114208A (en) 1976-03-22 1976-03-22 Multiple digital suppressor

Country Status (1)

Country Link
JP (1) JPS52114208A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008228397A (en) * 2007-03-09 2008-09-25 Mitsubishi Electric Corp Motor with encoder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008228397A (en) * 2007-03-09 2008-09-25 Mitsubishi Electric Corp Motor with encoder

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