JPS5177965U - - Google Patents
Info
- Publication number
- JPS5177965U JPS5177965U JP1974151455U JP15145574U JPS5177965U JP S5177965 U JPS5177965 U JP S5177965U JP 1974151455 U JP1974151455 U JP 1974151455U JP 15145574 U JP15145574 U JP 15145574U JP S5177965 U JPS5177965 U JP S5177965U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1974151455U JPS5337584Y2 (enExample) | 1974-12-16 | 1974-12-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1974151455U JPS5337584Y2 (enExample) | 1974-12-16 | 1974-12-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5177965U true JPS5177965U (enExample) | 1976-06-19 |
| JPS5337584Y2 JPS5337584Y2 (enExample) | 1978-09-12 |
Family
ID=28443081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1974151455U Expired JPS5337584Y2 (enExample) | 1974-12-16 | 1974-12-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5337584Y2 (enExample) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4944530U (enExample) * | 1972-07-19 | 1974-04-19 |
-
1974
- 1974-12-16 JP JP1974151455U patent/JPS5337584Y2/ja not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4944530U (enExample) * | 1972-07-19 | 1974-04-19 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5337584Y2 (enExample) | 1978-09-12 |