JPS5124859Y2 - - Google Patents
Info
- Publication number
- JPS5124859Y2 JPS5124859Y2 JP1972023418U JP2341872U JPS5124859Y2 JP S5124859 Y2 JPS5124859 Y2 JP S5124859Y2 JP 1972023418 U JP1972023418 U JP 1972023418U JP 2341872 U JP2341872 U JP 2341872U JP S5124859 Y2 JPS5124859 Y2 JP S5124859Y2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Moulding By Coating Moulds (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1972023418U JPS5124859Y2 (en) | 1972-02-28 | 1972-02-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1972023418U JPS5124859Y2 (en) | 1972-02-28 | 1972-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS4899059U JPS4899059U (en) | 1973-11-22 |
JPS5124859Y2 true JPS5124859Y2 (en) | 1976-06-25 |
Family
ID=27879600
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1972023418U Expired JPS5124859Y2 (en) | 1972-02-28 | 1972-02-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5124859Y2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5730866Y2 (en) * | 1974-11-07 | 1982-07-07 | ||
JP2578009B2 (en) * | 1990-06-12 | 1997-02-05 | シャープ株式会社 | Method for molding LED light emitting display element |
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1972
- 1972-02-28 JP JP1972023418U patent/JPS5124859Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS4899059U (en) | 1973-11-22 |