JPS512382A - - Google Patents
Info
- Publication number
- JPS512382A JPS512382A JP49071313A JP7131374A JPS512382A JP S512382 A JPS512382 A JP S512382A JP 49071313 A JP49071313 A JP 49071313A JP 7131374 A JP7131374 A JP 7131374A JP S512382 A JPS512382 A JP S512382A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP49071313A JPS512382A (ja) | 1974-06-24 | 1974-06-24 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP49071313A JPS512382A (ja) | 1974-06-24 | 1974-06-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS512382A true JPS512382A (ja) | 1976-01-09 |
Family
ID=13456984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP49071313A Pending JPS512382A (ja) | 1974-06-24 | 1974-06-24 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS512382A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185053A (ja) * | 1989-01-12 | 1990-07-19 | Shinko Electric Ind Co Ltd | フリップチップボンディング用基板 |
US5447886A (en) * | 1993-02-18 | 1995-09-05 | Sharp Kabushiki Kaisha | Method for mounting semiconductor chip on circuit board |
JP2004031474A (ja) * | 2002-06-24 | 2004-01-29 | Tdk Corp | 電子部品及びその製造方法 |
-
1974
- 1974-06-24 JP JP49071313A patent/JPS512382A/ja active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02185053A (ja) * | 1989-01-12 | 1990-07-19 | Shinko Electric Ind Co Ltd | フリップチップボンディング用基板 |
US5447886A (en) * | 1993-02-18 | 1995-09-05 | Sharp Kabushiki Kaisha | Method for mounting semiconductor chip on circuit board |
JP2004031474A (ja) * | 2002-06-24 | 2004-01-29 | Tdk Corp | 電子部品及びその製造方法 |