JPS51149712A - Data transmission circuit - Google Patents

Data transmission circuit

Info

Publication number
JPS51149712A
JPS51149712A JP50073584A JP7358475A JPS51149712A JP S51149712 A JPS51149712 A JP S51149712A JP 50073584 A JP50073584 A JP 50073584A JP 7358475 A JP7358475 A JP 7358475A JP S51149712 A JPS51149712 A JP S51149712A
Authority
JP
Japan
Prior art keywords
data transmission
transmission circuit
circuit
transmission
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50073584A
Other languages
Japanese (ja)
Inventor
Tetsuo Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP50073584A priority Critical patent/JPS51149712A/en
Publication of JPS51149712A publication Critical patent/JPS51149712A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To simplify the circuit composition and to improve the reliability of the data transmission circuit with the use of a timing circuit for the data holding of the receiving side without any need of synchronizing the transmission and receiving sides.
JP50073584A 1975-06-17 1975-06-17 Data transmission circuit Pending JPS51149712A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50073584A JPS51149712A (en) 1975-06-17 1975-06-17 Data transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50073584A JPS51149712A (en) 1975-06-17 1975-06-17 Data transmission circuit

Publications (1)

Publication Number Publication Date
JPS51149712A true JPS51149712A (en) 1976-12-22

Family

ID=13522489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50073584A Pending JPS51149712A (en) 1975-06-17 1975-06-17 Data transmission circuit

Country Status (1)

Country Link
JP (1) JPS51149712A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952948A (en) * 1982-09-20 1984-03-27 Nippon Telegr & Teleph Corp <Ntt> Code transmitting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952948A (en) * 1982-09-20 1984-03-27 Nippon Telegr & Teleph Corp <Ntt> Code transmitting system

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