JPS5113622B2 - - Google Patents
Info
- Publication number
- JPS5113622B2 JPS5113622B2 JP8560172A JP8560172A JPS5113622B2 JP S5113622 B2 JPS5113622 B2 JP S5113622B2 JP 8560172 A JP8560172 A JP 8560172A JP 8560172 A JP8560172 A JP 8560172A JP S5113622 B2 JPS5113622 B2 JP S5113622B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8560172A JPS5113622B2 (US07754267-20100713-C00021.png) | 1972-08-25 | 1972-08-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8560172A JPS5113622B2 (US07754267-20100713-C00021.png) | 1972-08-25 | 1972-08-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4941070A JPS4941070A (US07754267-20100713-C00021.png) | 1974-04-17 |
| JPS5113622B2 true JPS5113622B2 (US07754267-20100713-C00021.png) | 1976-05-01 |
Family
ID=13863332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8560172A Expired JPS5113622B2 (US07754267-20100713-C00021.png) | 1972-08-25 | 1972-08-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5113622B2 (US07754267-20100713-C00021.png) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5322521U (US07754267-20100713-C00021.png) * | 1976-08-05 | 1978-02-25 | ||
| JPH0732122U (ja) * | 1992-12-15 | 1995-06-16 | 月星工業株式会社 | 自走式駐車場のノンスリップ パネル |
-
1972
- 1972-08-25 JP JP8560172A patent/JPS5113622B2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5322521U (US07754267-20100713-C00021.png) * | 1976-08-05 | 1978-02-25 | ||
| JPH0732122U (ja) * | 1992-12-15 | 1995-06-16 | 月星工業株式会社 | 自走式駐車場のノンスリップ パネル |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS4941070A (US07754267-20100713-C00021.png) | 1974-04-17 |
