JPS51123549A - Frequency demultiply circuit - Google Patents

Frequency demultiply circuit

Info

Publication number
JPS51123549A
JPS51123549A JP4887075A JP4887075A JPS51123549A JP S51123549 A JPS51123549 A JP S51123549A JP 4887075 A JP4887075 A JP 4887075A JP 4887075 A JP4887075 A JP 4887075A JP S51123549 A JPS51123549 A JP S51123549A
Authority
JP
Japan
Prior art keywords
demultiply
circuit
frequency
gain
ratio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4887075A
Other languages
Japanese (ja)
Inventor
Kimitake Utsunomiya
Shoji Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4887075A priority Critical patent/JPS51123549A/en
Publication of JPS51123549A publication Critical patent/JPS51123549A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K25/00—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers
    • H03K25/02—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers comprising charge storage, e.g. capacitor without polarisation hysteresis
    • H03K25/04—Pulse counters with step-by-step integration and static storage; Analogous frequency dividers comprising charge storage, e.g. capacitor without polarisation hysteresis using auxiliary pulse generator triggered by the incoming pulses

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To gain demultiply circuit which has demultiply ratio of 1/odd number.
JP4887075A 1975-04-22 1975-04-22 Frequency demultiply circuit Pending JPS51123549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4887075A JPS51123549A (en) 1975-04-22 1975-04-22 Frequency demultiply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4887075A JPS51123549A (en) 1975-04-22 1975-04-22 Frequency demultiply circuit

Publications (1)

Publication Number Publication Date
JPS51123549A true JPS51123549A (en) 1976-10-28

Family

ID=12815310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4887075A Pending JPS51123549A (en) 1975-04-22 1975-04-22 Frequency demultiply circuit

Country Status (1)

Country Link
JP (1) JPS51123549A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04129317A (en) * 1990-09-20 1992-04-30 Nec Ic Microcomput Syst Ltd Oscillating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04129317A (en) * 1990-09-20 1992-04-30 Nec Ic Microcomput Syst Ltd Oscillating circuit

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