JPS5061178A - - Google Patents

Info

Publication number
JPS5061178A
JPS5061178A JP10829374A JP10829374A JPS5061178A JP S5061178 A JPS5061178 A JP S5061178A JP 10829374 A JP10829374 A JP 10829374A JP 10829374 A JP10829374 A JP 10829374A JP S5061178 A JPS5061178 A JP S5061178A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10829374A
Other languages
Japanese (ja)
Other versions
JPS5337184B2 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19732347940 external-priority patent/DE2347940C3/de
Application filed filed Critical
Publication of JPS5061178A publication Critical patent/JPS5061178A/ja
Publication of JPS5337184B2 publication Critical patent/JPS5337184B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Measurement Of Radiation (AREA)
  • Manipulation Of Pulses (AREA)
JP10829374A 1973-09-24 1974-09-19 Expired JPS5337184B2 (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732347940 DE2347940C3 (de) 1973-09-24 Schaltungsanordnung mit einem Umlaufspeicher zum Zählen von Impulsen und zur Durchführung von Additionen und Subtraktionen

Publications (2)

Publication Number Publication Date
JPS5061178A true JPS5061178A (ko) 1975-05-26
JPS5337184B2 JPS5337184B2 (ko) 1978-10-06

Family

ID=5893448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10829374A Expired JPS5337184B2 (ko) 1973-09-24 1974-09-19

Country Status (1)

Country Link
JP (1) JPS5337184B2 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH048082Y2 (ko) * 1986-07-29 1992-03-02

Also Published As

Publication number Publication date
DE2347940A1 (de) 1975-04-24
JPS5337184B2 (ko) 1978-10-06
DE2347940B2 (de) 1975-12-11

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