JPS5039842A - - Google Patents

Info

Publication number
JPS5039842A
JPS5039842A JP49078651A JP7865174A JPS5039842A JP S5039842 A JPS5039842 A JP S5039842A JP 49078651 A JP49078651 A JP 49078651A JP 7865174 A JP7865174 A JP 7865174A JP S5039842 A JPS5039842 A JP S5039842A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP49078651A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS5039842A publication Critical patent/JPS5039842A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Discrete Mathematics (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP49078651A 1973-07-09 1974-07-08 Pending JPS5039842A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00377312A US3800130A (en) 1973-07-09 1973-07-09 Fast fourier transform stage using floating point numbers

Publications (1)

Publication Number Publication Date
JPS5039842A true JPS5039842A (ja) 1975-04-12

Family

ID=23488593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49078651A Pending JPS5039842A (ja) 1973-07-09 1974-07-08

Country Status (4)

Country Link
US (1) US3800130A (ja)
JP (1) JPS5039842A (ja)
CA (1) CA1041212A (ja)
GB (1) GB1463420A (ja)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3961750A (en) * 1974-04-05 1976-06-08 Signetics Corporation Expandable parallel binary shifter/rotator
US3926367A (en) * 1974-09-27 1975-12-16 Us Navy Complex filters, convolvers, and multipliers
US3947670A (en) * 1974-11-22 1976-03-30 General Electric Company Signed multiplication logic
US3997771A (en) * 1975-05-05 1976-12-14 Honeywell Inc. Apparatus and method for performing an arithmetic operation and multibit shift
US4031377A (en) * 1975-08-25 1977-06-21 Nippon Gakki Seizo Kabushiki Kaisha Fast multiplier circuit employing shift circuitry responsive to two binary numbers the sum of which approximately equals the mantissa of the multiplier
US4086657A (en) * 1976-08-18 1978-04-25 The United States Of America As Represented By The Secretary Of The Air Force Five-stage four-bit complex multiplier
FR2413712A1 (fr) * 1977-12-30 1979-07-27 Ibm France Microprocesseur specialise pour le calcul de la somme de produits de deux operandes complexes
US4275452A (en) * 1979-11-08 1981-06-23 Rockwell International Corporation Simplified fast fourier transform butterfly arithmetic unit
US4354249A (en) * 1980-03-24 1982-10-12 Motorola Inc. Processing unit for multiplying two mathematical quantities including at least one complex multiplier
US4344151A (en) * 1980-04-21 1982-08-10 Rockwell International Corporation ROM-Based complex multiplier useful for FFT butterfly arithmetic unit
US4689762A (en) * 1984-09-10 1987-08-25 Sanders Associates, Inc. Dynamically configurable fast Fourier transform butterfly circuit
US4769779A (en) * 1985-12-16 1988-09-06 Texas Instruments Incorporated Systolic complex multiplier
US4858164A (en) * 1987-05-29 1989-08-15 United Technologies Corporation Complex arithmetic processing
US5303172A (en) * 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
US4996661A (en) * 1988-10-05 1991-02-26 United Technologies Corporation Single chip complex floating point numeric processor
US5339447A (en) * 1989-11-17 1994-08-16 Texas Instruments Incorporated Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data
US6411978B1 (en) * 1999-05-26 2002-06-25 Infineon Technologies Ag I. Gr. Mechanism for block floating point FFT hardware support on a fixed point digital signal processor
US7088791B2 (en) * 2001-10-19 2006-08-08 Texas Instruments Incorporated Systems and methods for improving FFT signal-to-noise ratio by identifying stage without bit growth
KR100925427B1 (ko) * 2002-12-27 2009-11-06 엘지전자 주식회사 채널 등화기
US7546329B2 (en) * 2003-09-29 2009-06-09 Broadcom Corporation Systems for performing multiplication operations on operands representing complex numbers
US7546330B2 (en) * 2003-09-30 2009-06-09 Broadcom Corporation Systems for performing multiply-accumulate operations on operands representing complex numbers
US7987222B1 (en) * 2004-04-22 2011-07-26 Altera Corporation Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
TWI237773B (en) * 2004-06-24 2005-08-11 Univ Nat Chiao Tung Fast fourier transform processor and dynamic scaling method thereof and radix-8 fast Fourier transform computation method
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US8266198B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8266199B2 (en) * 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
CN101825998B (zh) * 2010-01-22 2012-09-05 龙芯中科技术有限公司 向量复数乘法运算的处理方法及相应的装置
US8601044B2 (en) * 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8880847B2 (en) * 2010-09-28 2014-11-04 Texas Instruments Incorporated Multistream prefetch buffer
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8706794B1 (en) * 2011-08-23 2014-04-22 Gregory K. Fleizach No-multiply digital signal processing method
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
CN116719005B (zh) * 2023-08-10 2023-10-03 南京隼眼电子科技有限公司 基于fpga的定点数据处理方法、装置及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588460A (en) * 1968-07-01 1971-06-28 Bell Telephone Labor Inc Fast fourier transform processor
US3673399A (en) * 1970-05-28 1972-06-27 Ibm Fft processor with unique addressing
US3697734A (en) * 1970-07-28 1972-10-10 Singer Co Digital computer utilizing a plurality of parallel asynchronous arithmetic units
US3725649A (en) * 1971-10-01 1973-04-03 Raytheon Co Floating point number processor for a digital computer
US3761698A (en) * 1972-04-24 1973-09-25 Texas Instruments Inc Combined digital multiplication summation

Also Published As

Publication number Publication date
GB1463420A (en) 1977-02-02
CA1041212A (en) 1978-10-24
DE2432979A1 (de) 1975-01-30
DE2432979B2 (de) 1976-11-04
US3800130A (en) 1974-03-26

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