JPS50147667A - - Google Patents

Info

Publication number
JPS50147667A
JPS50147667A JP49054736A JP5473674A JPS50147667A JP S50147667 A JPS50147667 A JP S50147667A JP 49054736 A JP49054736 A JP 49054736A JP 5473674 A JP5473674 A JP 5473674A JP S50147667 A JPS50147667 A JP S50147667A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP49054736A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP49054736A priority Critical patent/JPS50147667A/ja
Publication of JPS50147667A publication Critical patent/JPS50147667A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP49054736A 1974-05-16 1974-05-16 Pending JPS50147667A (enExample)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP49054736A JPS50147667A (enExample) 1974-05-16 1974-05-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49054736A JPS50147667A (enExample) 1974-05-16 1974-05-16

Publications (1)

Publication Number Publication Date
JPS50147667A true JPS50147667A (enExample) 1975-11-26

Family

ID=12979060

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49054736A Pending JPS50147667A (enExample) 1974-05-16 1974-05-16

Country Status (1)

Country Link
JP (1) JPS50147667A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145464U (enExample) * 1977-03-25 1978-11-16
JPS5423568U (enExample) * 1977-07-19 1979-02-16
JPS54172765U (enExample) * 1978-05-25 1979-12-06
JPS5787542U (enExample) * 1980-11-14 1982-05-29
JPS5851525A (ja) * 1981-09-22 1983-03-26 Oki Electric Ind Co Ltd 半導体装置及びその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53145464U (enExample) * 1977-03-25 1978-11-16
JPS5423568U (enExample) * 1977-07-19 1979-02-16
JPS54172765U (enExample) * 1978-05-25 1979-12-06
JPS5787542U (enExample) * 1980-11-14 1982-05-29
JPS5851525A (ja) * 1981-09-22 1983-03-26 Oki Electric Ind Co Ltd 半導体装置及びその製造方法

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