JPS50110746A - - Google Patents
Info
- Publication number
- JPS50110746A JPS50110746A JP1481375A JP1481375A JPS50110746A JP S50110746 A JPS50110746 A JP S50110746A JP 1481375 A JP1481375 A JP 1481375A JP 1481375 A JP1481375 A JP 1481375A JP S50110746 A JPS50110746 A JP S50110746A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US439677A US3900837A (en) | 1974-02-04 | 1974-02-04 | Variably addressable semiconductor mass memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS50110746A true JPS50110746A (US20030204162A1-20031030-M00001.png) | 1975-09-01 |
| JPS5811710B2 JPS5811710B2 (ja) | 1983-03-04 |
Family
ID=23745691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50014813A Expired JPS5811710B2 (ja) | 1974-02-04 | 1975-02-04 | シユウセキカイロガタキオクソウチ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US3900837A (US20030204162A1-20031030-M00001.png) |
| JP (1) | JPS5811710B2 (US20030204162A1-20031030-M00001.png) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4038648A (en) * | 1974-06-03 | 1977-07-26 | Chesley Gilman D | Self-configurable circuit structure for achieving wafer scale integration |
| US4194130A (en) * | 1977-11-21 | 1980-03-18 | Motorola, Inc. | Digital predecoding system |
| GB2082354B (en) * | 1980-08-21 | 1984-04-11 | Burroughs Corp | Improvements in or relating to wafer-scale integrated circuits |
| US4419746A (en) * | 1980-10-14 | 1983-12-06 | Texas Instruments Incorporated | Multiple pointer memory system |
| US4601019B1 (en) * | 1983-08-31 | 1997-09-30 | Texas Instruments Inc | Memory with redundancy |
| IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Introductory / Origin Circuit Agreed Using High-Performance Brokerage |
| US5574688A (en) * | 1995-05-10 | 1996-11-12 | Sgs-Thomson Microelectronics, Inc. | Apparatus and method for mapping a redundant memory column to a defective memory column |
| DE10008578A1 (de) * | 2000-02-24 | 2001-09-06 | Infineon Technologies Ag | Redundanz-Multiplexer für Halbleiterspeicheranordnung |
| US6643736B1 (en) * | 2000-08-29 | 2003-11-04 | Arm Limited | Scratch pad memories |
| US7085658B2 (en) * | 2004-10-20 | 2006-08-01 | International Business Machines Corporation | Method and apparatus for rapid inline measurement of parameter spreads and defects in integrated circuit chips |
| JP6210187B2 (ja) * | 2012-10-23 | 2017-10-11 | セイコーエプソン株式会社 | 集積回路装置、物理量測定装置、電子機器および移動体 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3798617A (en) * | 1970-11-04 | 1974-03-19 | Gen Instrument Corp | Permanent storage memory and means for addressing |
| US3781826A (en) * | 1971-11-15 | 1973-12-25 | Ibm | Monolithic memory utilizing defective storage cells |
| US3800294A (en) * | 1973-06-13 | 1974-03-26 | Ibm | System for improving the reliability of systems using dirty memories |
-
1974
- 1974-02-04 US US439677A patent/US3900837A/en not_active Expired - Lifetime
-
1975
- 1975-02-04 JP JP50014813A patent/JPS5811710B2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5811710B2 (ja) | 1983-03-04 |
| US3900837A (en) | 1975-08-19 |
