JPS4990472A - - Google Patents

Info

Publication number
JPS4990472A
JPS4990472A JP48138509A JP13850973A JPS4990472A JP S4990472 A JPS4990472 A JP S4990472A JP 48138509 A JP48138509 A JP 48138509A JP 13850973 A JP13850973 A JP 13850973A JP S4990472 A JPS4990472 A JP S4990472A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP48138509A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4990472A publication Critical patent/JPS4990472A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP48138509A 1972-12-13 1973-12-11 Pending JPS4990472A (ref)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00314658A US3806822A (en) 1972-12-13 1972-12-13 Phase locked loop employing gated alternating current injection for fast synchronization

Publications (1)

Publication Number Publication Date
JPS4990472A true JPS4990472A (ref) 1974-08-29

Family

ID=23220894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48138509A Pending JPS4990472A (ref) 1972-12-13 1973-12-11

Country Status (2)

Country Link
US (1) US3806822A (ref)
JP (1) JPS4990472A (ref)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3971021A (en) * 1975-04-14 1976-07-20 Sanders Associates, Inc. Coherent frequency memory
FR2466919A1 (fr) * 1979-09-27 1981-04-10 Communications Satellite Corp Reseau de retablissement d'horloge pour modems qpsk
US4305041A (en) * 1979-10-26 1981-12-08 Rockwell International Corporation Time compensated clock oscillator
US4949197A (en) * 1988-09-08 1990-08-14 Aspen Peripherals Corp. Dead track acquisition for phase-locked loop control
EP0420667B1 (en) * 1989-09-29 1997-08-06 Kabushiki Kaisha Toshiba Phase-synchronous controller for production of reference clock signal in a disk drive system
US5579348A (en) * 1994-02-02 1996-11-26 Gi Corporation Method and apparatus for improving the apparent accuracy of a data receiver clock circuit
DE10044835C2 (de) * 2000-09-11 2002-11-21 Infineon Technologies Ag Taktregenerierungsschaltung zum Regenerieren von Eingangsdaten und Verfahren zur Nutzung

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2740046A (en) * 1950-11-25 1956-03-27 Philco Corp Signal control circuit
GB886434A (en) * 1959-04-08 1962-01-10 British Broadcasting Corp Improvements in oscillator synchronisation circuits
US3460052A (en) * 1967-08-02 1969-08-05 Information Dev Corp Oscillator phase and frequency synchronizing circuit
US3701953A (en) * 1970-11-16 1972-10-31 Telecommunications Technology Digital phase lock loop circuit employing oscillator triggered at zero voltage crossing of input signal

Also Published As

Publication number Publication date
US3806822A (en) 1974-04-23

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