JPS4975065A - - Google Patents

Info

Publication number
JPS4975065A
JPS4975065A JP48111558A JP11155873A JPS4975065A JP S4975065 A JPS4975065 A JP S4975065A JP 48111558 A JP48111558 A JP 48111558A JP 11155873 A JP11155873 A JP 11155873A JP S4975065 A JPS4975065 A JP S4975065A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP48111558A
Other languages
Japanese (ja)
Other versions
JPS5428073B2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US298729A external-priority patent/US3877051A/en
Application filed filed Critical
Publication of JPS4975065A publication Critical patent/JPS4975065A/ja
Publication of JPS5428073B2 publication Critical patent/JPS5428073B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP11155873A 1972-10-18 1973-10-05 Expired JPS5428073B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US298729A US3877051A (en) 1972-10-18 1972-10-18 Multilayer insulation integrated circuit structure

Publications (2)

Publication Number Publication Date
JPS4975065A true JPS4975065A (en) 1974-07-19
JPS5428073B2 JPS5428073B2 (en) 1979-09-13

Family

ID=23151792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11155873A Expired JPS5428073B2 (en) 1972-10-18 1973-10-05

Country Status (5)

Country Link
JP (1) JPS5428073B2 (en)
DD (1) DD109476A5 (en)
ES (1) ES418485A1 (en)
IT (1) IT1001545B (en)
SE (1) SE386308B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519857A (en) * 1978-07-28 1980-02-12 Nec Corp Semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5519857A (en) * 1978-07-28 1980-02-12 Nec Corp Semiconductor

Also Published As

Publication number Publication date
DD109476A5 (en) 1974-11-05
ES418485A1 (en) 1976-04-16
SE7312846L (en) 1974-04-19
IT1001545B (en) 1976-04-30
SE386308B (en) 1976-08-02
JPS5428073B2 (en) 1979-09-13

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