JPS4958097A - - Google Patents

Info

Publication number
JPS4958097A
JPS4958097A JP48086442A JP8644273A JPS4958097A JP S4958097 A JPS4958097 A JP S4958097A JP 48086442 A JP48086442 A JP 48086442A JP 8644273 A JP8644273 A JP 8644273A JP S4958097 A JPS4958097 A JP S4958097A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP48086442A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4958097A publication Critical patent/JPS4958097A/ja
Pending legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B33/00—Silicon; Compounds thereof
    • C01B33/113—Silicon oxides; Hydrates thereof
    • C01B33/12—Silica; Hydrates thereof, e.g. lepidoic silicic acid
    • C01B33/14—Colloidal silica, e.g. dispersions, gels, sols
    • C01B33/145—Preparation of hydroorganosols, organosols or dispersions in an organic medium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Formation Of Insulating Films (AREA)
  • Glass Compositions (AREA)
  • Silicon Compounds (AREA)
JP48086442A 1972-08-08 1973-08-02 Pending JPS4958097A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00278833A US3832202A (en) 1972-08-08 1972-08-08 Liquid silica source for semiconductors liquid silica source for semiconductors

Publications (1)

Publication Number Publication Date
JPS4958097A true JPS4958097A (ja) 1974-06-05

Family

ID=23066563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP48086442A Pending JPS4958097A (ja) 1972-08-08 1973-08-02

Country Status (5)

Country Link
US (1) US3832202A (ja)
JP (1) JPS4958097A (ja)
DE (1) DE2338079A1 (ja)
FR (1) FR2195587A1 (ja)
GB (1) GB1401707A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111597A (en) * 1974-07-19 1976-01-29 Hitachi Ltd Ekishohyojibanno seizohoho

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3892608A (en) * 1974-02-28 1975-07-01 Motorola Inc Method for filling grooves and moats used on semiconductor devices
US3969168A (en) * 1974-02-28 1976-07-13 Motorola, Inc. Method for filling grooves and moats used on semiconductor devices
JPS5253679A (en) * 1975-10-29 1977-04-30 Hitachi Ltd Productin of semiconductor device
US4222792A (en) * 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
JPS5676538A (en) * 1979-11-28 1981-06-24 Sumitomo Electric Ind Ltd Formation of insulating film on semiconductor substrate
DE3704518A1 (de) * 1987-02-13 1988-08-25 Hoechst Ag Beschichtungsloesung und verfahren zur erzeugung glasartiger schichten
US4798629A (en) * 1987-10-22 1989-01-17 Motorola Inc. Spin-on glass for use in semiconductor processing
US5152834A (en) * 1990-09-14 1992-10-06 Ncr Corporation Spin-on glass composition
US5302198A (en) * 1990-09-14 1994-04-12 Ncr Corporation Coating solution for forming glassy layers
US5472488A (en) * 1990-09-14 1995-12-05 Hyundai Electronics America Coating solution for forming glassy layers
US5527872A (en) * 1990-09-14 1996-06-18 At&T Global Information Solutions Company Electronic device with a spin-on glass dielectric layer
US6303047B1 (en) * 1999-03-22 2001-10-16 Lsi Logic Corporation Low dielectric constant multiple carbon-containing silicon oxide dielectric material for use in integrated circuit structures, and method of making same
US6524974B1 (en) 1999-03-22 2003-02-25 Lsi Logic Corporation Formation of improved low dielectric constant carbon-containing silicon oxide dielectric material by reaction of carbon-containing silane with oxidizing agent in the presence of one or more reaction retardants
US6204192B1 (en) 1999-03-29 2001-03-20 Lsi Logic Corporation Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures
US6232658B1 (en) 1999-06-30 2001-05-15 Lsi Logic Corporation Process to prevent stress cracking of dielectric films on semiconductor wafers
US6114259A (en) * 1999-07-27 2000-09-05 Lsi Logic Corporation Process for treating exposed surfaces of a low dielectric constant carbon doped silicon oxide dielectric material to protect the material from damage
US6391795B1 (en) 1999-10-22 2002-05-21 Lsi Logic Corporation Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning
US6423628B1 (en) 1999-10-22 2002-07-23 Lsi Logic Corporation Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
US6756674B1 (en) 1999-10-22 2004-06-29 Lsi Logic Corporation Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same
US6316354B1 (en) 1999-10-26 2001-11-13 Lsi Logic Corporation Process for removing resist mask of integrated circuit structure which mitigates damage to underlying low dielectric constant silicon oxide dielectric layer
US6147012A (en) * 1999-11-12 2000-11-14 Lsi Logic Corporation Process for forming low k silicon oxide dielectric material while suppressing pressure spiking and inhibiting increase in dielectric constant
US6346490B1 (en) 2000-04-05 2002-02-12 Lsi Logic Corporation Process for treating damaged surfaces of low k carbon doped silicon oxide dielectric material after plasma etching and plasma cleaning steps
US6506678B1 (en) 2000-05-19 2003-01-14 Lsi Logic Corporation Integrated circuit structures having low k porous aluminum oxide dielectric material separating aluminum lines, and method of making same
US6426286B1 (en) 2000-05-19 2002-07-30 Lsi Logic Corporation Interconnection system with lateral barrier layer
US6492731B1 (en) 2000-06-27 2002-12-10 Lsi Logic Corporation Composite low dielectric constant film for integrated circuit structure
US6346488B1 (en) 2000-06-27 2002-02-12 Lsi Logic Corporation Process to provide enhanced resistance to cracking and to further reduce the dielectric constant of a low dielectric constant dielectric film of an integrated circuit structure by implantation with hydrogen ions
US6368979B1 (en) 2000-06-28 2002-04-09 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6350700B1 (en) 2000-06-28 2002-02-26 Lsi Logic Corporation Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure
US6489242B1 (en) 2000-09-13 2002-12-03 Lsi Logic Corporation Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures
US6391768B1 (en) 2000-10-30 2002-05-21 Lsi Logic Corporation Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure
US6423630B1 (en) 2000-10-31 2002-07-23 Lsi Logic Corporation Process for forming low K dielectric material between metal lines
US6537923B1 (en) 2000-10-31 2003-03-25 Lsi Logic Corporation Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6420277B1 (en) 2000-11-01 2002-07-16 Lsi Logic Corporation Process for inhibiting crack formation in low dielectric constant dielectric films of integrated circuit structure
US6858195B2 (en) 2001-02-23 2005-02-22 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material
US6572925B2 (en) 2001-02-23 2003-06-03 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon containing silicon oxide dielectric material
US6649219B2 (en) 2001-02-23 2003-11-18 Lsi Logic Corporation Process for forming a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material characterized by improved resistance to oxidation
US6503840B2 (en) 2001-05-02 2003-01-07 Lsi Logic Corporation Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning
US6559048B1 (en) 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
US6583026B1 (en) 2001-05-31 2003-06-24 Lsi Logic Corporation Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
US6562700B1 (en) 2001-05-31 2003-05-13 Lsi Logic Corporation Process for removal of resist mask over low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and removal of residues from via etch and resist mask removal
US6566171B1 (en) 2001-06-12 2003-05-20 Lsi Logic Corporation Fuse construction for integrated circuit structure having low dielectric constant dielectric material
US6930056B1 (en) * 2001-06-19 2005-08-16 Lsi Logic Corporation Plasma treatment of low dielectric constant dielectric material to form structures useful in formation of metal interconnects and/or filled vias for integrated circuit structure
US6559033B1 (en) 2001-06-27 2003-05-06 Lsi Logic Corporation Processing for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal lines
US6673721B1 (en) * 2001-07-02 2004-01-06 Lsi Logic Corporation Process for removal of photoresist mask used for making vias in low k carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask
US6723653B1 (en) 2001-08-17 2004-04-20 Lsi Logic Corporation Process for reducing defects in copper-filled vias and/or trenches formed in porous low-k dielectric material
US6881664B2 (en) * 2001-08-28 2005-04-19 Lsi Logic Corporation Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
US6613665B1 (en) 2001-10-26 2003-09-02 Lsi Logic Corporation Process for forming integrated circuit structure comprising layer of low k dielectric material having antireflective properties in an upper surface
US6528423B1 (en) 2001-10-26 2003-03-04 Lsi Logic Corporation Process for forming composite of barrier layers of dielectric material to inhibit migration of copper from copper metal interconnect of integrated circuit structure into adjacent layer of low k dielectric material

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5111597A (en) * 1974-07-19 1976-01-29 Hitachi Ltd Ekishohyojibanno seizohoho
JPS5510179B2 (ja) * 1974-07-19 1980-03-14

Also Published As

Publication number Publication date
FR2195587A1 (ja) 1974-03-08
DE2338079A1 (de) 1974-02-28
GB1401707A (en) 1975-07-30
US3832202A (en) 1974-08-27

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