JPS4944639A - - Google Patents

Info

Publication number
JPS4944639A
JPS4944639A JP47086893A JP8689372A JPS4944639A JP S4944639 A JPS4944639 A JP S4944639A JP 47086893 A JP47086893 A JP 47086893A JP 8689372 A JP8689372 A JP 8689372A JP S4944639 A JPS4944639 A JP S4944639A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP47086893A
Other languages
Japanese (ja)
Other versions
JPS5242502B2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP47086893A priority Critical patent/JPS5242502B2/ja
Priority to US00389535A priority patent/US3829710A/en
Priority to CA179,237A priority patent/CA979080A/en
Priority to GB3962973A priority patent/GB1418083A/en
Priority to AU59527/73A priority patent/AU478145B2/en
Priority to CH1248173A priority patent/CH569393A5/xx
Priority to IT52254/73A priority patent/IT994173B/it
Priority to DE19732343805 priority patent/DE2343805C3/de
Priority to FR7331375A priority patent/FR2198325B1/fr
Publication of JPS4944639A publication Critical patent/JPS4944639A/ja
Publication of JPS5242502B2 publication Critical patent/JPS5242502B2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
JP47086893A 1972-08-30 1972-08-30 Expired JPS5242502B2 (en:Method)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP47086893A JPS5242502B2 (en:Method) 1972-08-30 1972-08-30
US00389535A US3829710A (en) 1972-08-30 1973-08-20 Logic circuit arrangement using insulated gate field effect transistors
CA179,237A CA979080A (en) 1972-08-30 1973-08-20 Logic circuit arrangement using insulated gate field effect transistors
GB3962973A GB1418083A (en) 1972-08-30 1973-08-21 Logic circuit arrangement using insulated gate field effect transistors
AU59527/73A AU478145B2 (en) 1972-08-30 1973-08-22 A logic circuit arrangement using insulated gate field effect transistors
CH1248173A CH569393A5 (en:Method) 1972-08-30 1973-08-30
IT52254/73A IT994173B (it) 1972-08-30 1973-08-30 Sistemazione di circuito logico che usa transistor i g detti anche transistor ad effetto di campo a griglia isolata
DE19732343805 DE2343805C3 (de) 1972-08-30 1973-08-30 Logische Schaltungsanordnung
FR7331375A FR2198325B1 (en:Method) 1972-08-30 1973-08-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47086893A JPS5242502B2 (en:Method) 1972-08-30 1972-08-30

Publications (2)

Publication Number Publication Date
JPS4944639A true JPS4944639A (en:Method) 1974-04-26
JPS5242502B2 JPS5242502B2 (en:Method) 1977-10-25

Family

ID=13899503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP47086893A Expired JPS5242502B2 (en:Method) 1972-08-30 1972-08-30

Country Status (1)

Country Link
JP (1) JPS5242502B2 (en:Method)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861708U (ja) * 1981-10-22 1983-04-26 新日本製鐵株式会社 包装バンド切断装置
JPH0369609U (en:Method) * 1989-11-14 1991-07-11

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5861708U (ja) * 1981-10-22 1983-04-26 新日本製鐵株式会社 包装バンド切断装置
JPH0369609U (en:Method) * 1989-11-14 1991-07-11

Also Published As

Publication number Publication date
JPS5242502B2 (en:Method) 1977-10-25

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