JPS4940669A - - Google Patents
Info
- Publication number
- JPS4940669A JPS4940669A JP8471972A JP8471972A JPS4940669A JP S4940669 A JPS4940669 A JP S4940669A JP 8471972 A JP8471972 A JP 8471972A JP 8471972 A JP8471972 A JP 8471972A JP S4940669 A JPS4940669 A JP S4940669A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8471972A JPS5719572B2 (en:Method) | 1972-08-23 | 1972-08-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8471972A JPS5719572B2 (en:Method) | 1972-08-23 | 1972-08-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS4940669A true JPS4940669A (en:Method) | 1974-04-16 |
| JPS5719572B2 JPS5719572B2 (en:Method) | 1982-04-23 |
Family
ID=13838475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8471972A Expired JPS5719572B2 (en:Method) | 1972-08-23 | 1972-08-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5719572B2 (en:Method) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272639A (ja) * | 1988-09-07 | 1990-03-12 | Rohm Co Ltd | ダイボンディング用半田層の形成方法 |
-
1972
- 1972-08-23 JP JP8471972A patent/JPS5719572B2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0272639A (ja) * | 1988-09-07 | 1990-03-12 | Rohm Co Ltd | ダイボンディング用半田層の形成方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5719572B2 (en:Method) | 1982-04-23 |