JPS4895774A - - Google Patents
Info
- Publication number
- JPS4895774A JPS4895774A JP47028314A JP2831472A JPS4895774A JP S4895774 A JPS4895774 A JP S4895774A JP 47028314 A JP47028314 A JP 47028314A JP 2831472 A JP2831472 A JP 2831472A JP S4895774 A JPS4895774 A JP S4895774A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47028314A JPS4895774A (cs) | 1972-03-17 | 1972-03-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP47028314A JPS4895774A (cs) | 1972-03-17 | 1972-03-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS4895774A true JPS4895774A (cs) | 1973-12-07 |
Family
ID=12245140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP47028314A Pending JPS4895774A (cs) | 1972-03-17 | 1972-03-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS4895774A (cs) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5920633U (ja) * | 1982-07-30 | 1984-02-08 | 富士通株式会社 | バンプ接合型半導体装置 |
-
1972
- 1972-03-17 JP JP47028314A patent/JPS4895774A/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5920633U (ja) * | 1982-07-30 | 1984-02-08 | 富士通株式会社 | バンプ接合型半導体装置 |