JPS4847775A - - Google Patents

Info

Publication number
JPS4847775A
JPS4847775A JP8257271A JP8257271A JPS4847775A JP S4847775 A JPS4847775 A JP S4847775A JP 8257271 A JP8257271 A JP 8257271A JP 8257271 A JP8257271 A JP 8257271A JP S4847775 A JPS4847775 A JP S4847775A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8257271A
Other languages
Japanese (ja)
Other versions
JPS514901B2 (en:Method
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8257271A priority Critical patent/JPS514901B2/ja
Publication of JPS4847775A publication Critical patent/JPS4847775A/ja
Publication of JPS514901B2 publication Critical patent/JPS514901B2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP8257271A 1971-10-18 1971-10-18 Expired JPS514901B2 (en:Method)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8257271A JPS514901B2 (en:Method) 1971-10-18 1971-10-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8257271A JPS514901B2 (en:Method) 1971-10-18 1971-10-18

Publications (2)

Publication Number Publication Date
JPS4847775A true JPS4847775A (en:Method) 1973-07-06
JPS514901B2 JPS514901B2 (en:Method) 1976-02-16

Family

ID=13778185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8257271A Expired JPS514901B2 (en:Method) 1971-10-18 1971-10-18

Country Status (1)

Country Link
JP (1) JPS514901B2 (en:Method)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5052467U (en:Method) * 1973-09-10 1975-05-20

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54174804U (en:Method) * 1978-05-31 1979-12-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5052467U (en:Method) * 1973-09-10 1975-05-20

Also Published As

Publication number Publication date
JPS514901B2 (en:Method) 1976-02-16

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