JPS4833355A - - Google Patents

Info

Publication number
JPS4833355A
JPS4833355A JP6658671A JP6658671A JPS4833355A JP S4833355 A JPS4833355 A JP S4833355A JP 6658671 A JP6658671 A JP 6658671A JP 6658671 A JP6658671 A JP 6658671A JP S4833355 A JPS4833355 A JP S4833355A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6658671A
Other languages
Japanese (ja)
Other versions
JPS5310262B2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6658671A priority Critical patent/JPS5310262B2/ja
Publication of JPS4833355A publication Critical patent/JPS4833355A/ja
Publication of JPS5310262B2 publication Critical patent/JPS5310262B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Laminated Bodies (AREA)
  • Blow-Moulding Or Thermoforming Of Plastics Or The Like (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
JP6658671A 1971-09-01 1971-09-01 Expired JPS5310262B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6658671A JPS5310262B2 (en) 1971-09-01 1971-09-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6658671A JPS5310262B2 (en) 1971-09-01 1971-09-01

Publications (2)

Publication Number Publication Date
JPS4833355A true JPS4833355A (en) 1973-05-09
JPS5310262B2 JPS5310262B2 (en) 1978-04-12

Family

ID=13320182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6658671A Expired JPS5310262B2 (en) 1971-09-01 1971-09-01

Country Status (1)

Country Link
JP (1) JPS5310262B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50133455A (en) * 1974-04-15 1975-10-22
JPS50140859A (en) * 1974-04-30 1975-11-12
JPS5553498A (en) * 1978-10-14 1980-04-18 Matsushita Electric Works Ltd Method of manufacturing multilayer printed circuit board
JPH03191595A (en) * 1989-12-20 1991-08-21 Risho Kogyo Co Ltd Manufacture of one-sided metal-clad laminated board for multilayer circuit board use

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54145168U (en) * 1978-03-31 1979-10-08

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3400018A (en) * 1963-03-29 1968-09-03 Formica Int Handling laminating plates

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3400018A (en) * 1963-03-29 1968-09-03 Formica Int Handling laminating plates

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50133455A (en) * 1974-04-15 1975-10-22
JPS50140859A (en) * 1974-04-30 1975-11-12
JPS5553498A (en) * 1978-10-14 1980-04-18 Matsushita Electric Works Ltd Method of manufacturing multilayer printed circuit board
JPH03191595A (en) * 1989-12-20 1991-08-21 Risho Kogyo Co Ltd Manufacture of one-sided metal-clad laminated board for multilayer circuit board use

Also Published As

Publication number Publication date
JPS5310262B2 (en) 1978-04-12

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