JPS475124U - - Google Patents
Info
- Publication number
- JPS475124U JPS475124U JP494371U JP494371U JPS475124U JP S475124 U JPS475124 U JP S475124U JP 494371 U JP494371 U JP 494371U JP 494371 U JP494371 U JP 494371U JP S475124 U JPS475124 U JP S475124U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Hinges (AREA)
- Cabinets, Racks, Or The Like Of Rigid Construction (AREA)
- Furniture Connections (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP494371U JPS51424Y2 (enrdf_load_stackoverflow) | 1971-02-02 | 1971-02-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP494371U JPS51424Y2 (enrdf_load_stackoverflow) | 1971-02-02 | 1971-02-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS475124U true JPS475124U (enrdf_load_stackoverflow) | 1972-09-14 |
| JPS51424Y2 JPS51424Y2 (enrdf_load_stackoverflow) | 1976-01-08 |
Family
ID=27845470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP494371U Expired JPS51424Y2 (enrdf_load_stackoverflow) | 1971-02-02 | 1971-02-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS51424Y2 (enrdf_load_stackoverflow) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7265399B2 (en) | 2004-10-29 | 2007-09-04 | Cree, Inc. | Asymetric layout structures for transistors and methods of fabricating the same |
| US7297580B2 (en) | 2002-11-26 | 2007-11-20 | Cree, Inc. | Methods of fabricating transistors having buried p-type layers beneath the source region |
| US7326962B2 (en) | 2004-12-15 | 2008-02-05 | Cree, Inc. | Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same |
| US7348612B2 (en) | 2004-10-29 | 2008-03-25 | Cree, Inc. | Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same |
| US7402844B2 (en) | 2005-11-29 | 2008-07-22 | Cree, Inc. | Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods |
| US7646043B2 (en) | 2006-09-28 | 2010-01-12 | Cree, Inc. | Transistors having buried p-type layers coupled to the gate |
-
1971
- 1971-02-02 JP JP494371U patent/JPS51424Y2/ja not_active Expired
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7297580B2 (en) | 2002-11-26 | 2007-11-20 | Cree, Inc. | Methods of fabricating transistors having buried p-type layers beneath the source region |
| US7265399B2 (en) | 2004-10-29 | 2007-09-04 | Cree, Inc. | Asymetric layout structures for transistors and methods of fabricating the same |
| US7348612B2 (en) | 2004-10-29 | 2008-03-25 | Cree, Inc. | Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same |
| US7326962B2 (en) | 2004-12-15 | 2008-02-05 | Cree, Inc. | Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same |
| US7402844B2 (en) | 2005-11-29 | 2008-07-22 | Cree, Inc. | Metal semiconductor field effect transistors (MESFETS) having channels of varying thicknesses and related methods |
| US7646043B2 (en) | 2006-09-28 | 2010-01-12 | Cree, Inc. | Transistors having buried p-type layers coupled to the gate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS51424Y2 (enrdf_load_stackoverflow) | 1976-01-08 |