JPS459628Y1 - - Google Patents
Info
- Publication number
- JPS459628Y1 JPS459628Y1 JP1967060599U JP6059967U JPS459628Y1 JP S459628 Y1 JPS459628 Y1 JP S459628Y1 JP 1967060599 U JP1967060599 U JP 1967060599U JP 6059967 U JP6059967 U JP 6059967U JP S459628 Y1 JPS459628 Y1 JP S459628Y1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1967060599U JPS459628Y1 (enrdf_load_stackoverflow) | 1967-07-14 | 1967-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1967060599U JPS459628Y1 (enrdf_load_stackoverflow) | 1967-07-14 | 1967-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS459628Y1 true JPS459628Y1 (enrdf_load_stackoverflow) | 1970-05-06 |
Family
ID=42838549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1967060599U Expired JPS459628Y1 (enrdf_load_stackoverflow) | 1967-07-14 | 1967-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS459628Y1 (enrdf_load_stackoverflow) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5038446U (enrdf_load_stackoverflow) * | 1973-08-08 | 1975-04-21 | ||
| JPS5038445U (enrdf_load_stackoverflow) * | 1973-08-08 | 1975-04-21 |
-
1967
- 1967-07-14 JP JP1967060599U patent/JPS459628Y1/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5038446U (enrdf_load_stackoverflow) * | 1973-08-08 | 1975-04-21 | ||
| JPS5038445U (enrdf_load_stackoverflow) * | 1973-08-08 | 1975-04-21 |