JPH1197633A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of realizing high- speed accessings by reducing variations in the lengths of internal I/O buses and by minimizing interconnection loads. SOLUTION: In a 64M-bit SDRAM semiconductor chip, which is a semiconductor storage device of a TSOP structure constructed of a 54-pin LOC and comprises four banks 0 to 3, the arrangement of internal I/O buses is taken into consideration in assigning I/O terminals to a memory map. In each bank that is halved, I/O terminals are assigned from 0 to C from the right end at a bank 0 on the right side, and I/O terminals are assigned from 4 to 8 from the right end at the bank 0 on the left side. I/O terminals are similarly assigned to the banks 1 to 3. Further, in the banks on the upper side, the terminals 0 to C of the bank 0 to the right side are connected to the terminals 0 to C of the bank 2 on the right side, and the terminals 4 to 8 of the bank 0 on the left side to the corresponding terminals 4 to 8 of the bank 2 on the left side via internal I/O buses IO bus. The banks 1 and 3 on the lower side are also connected similarly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly, to a synchronous DRAM (SDRAM),
The present invention relates to a technology effective when applied to a semiconductor memory device suitable for speeding up access in consideration of IO allocation of memory mats and arrangement of internal IO buses in a DRAM or the like.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, an SDRAM as an example of a semiconductor memory device is also called a synchronous DRAM, and is suitable for high-speed operation by controlling perfect synchronization by an external clock signal. A normal SDRAM has a plurality of banks, and a user can treat each bank as an independent memory. A 2-bank system is used for 16M bits, a 4-bank system is used for 64M bits, and a 4 to 8 bank system is mainly used for 256M bits. Have been.

Incidentally, as a technique relating to such a semiconductor memory device such as an SDRAM, for example,
"Advanced Electronics I-9 Ultra LSI Memory" published by Baifukan Co., Ltd. on January 5, P344-P3
48 and the like.

[0004]

In the above-mentioned semiconductor memory device such as an SDRAM, the internal IO bus is not taken into account in the IO allocation of the memory mat, and the internal IO bus length becomes unbalanced. ing.
In other words, the IO allocation of the memory mat largely depends on the internal configuration of the memory mat.
There is a need for a design technique that takes into account the internal IO bus for IO allocation of memory mats.

Therefore, an object of the present invention is to consider the arrangement of an internal IO bus in IO allocation of a memory mat,
An object of the present invention is to provide a semiconductor memory device capable of realizing high-speed access by minimizing variation in bus length and minimizing wiring load.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor memory device of the present invention, when the arrangement of the external terminals of the lead frame is predetermined, the arrangement of the bonding pads on the semiconductor chip is determined in accordance with the arrangement of the external terminals. In accordance with the arrangement of these bonding pads, each internal IO connecting each bonding pad to an IO line of the corresponding memory mat is provided.
The IO of the memory mat is allocated so as to make the bus wiring length uniform.

At this time, the IOs of the memory mats are arranged such that the bonding pads on one side / other side on the semiconductor chip are connected to one side / other side of the memory mat so as to minimize the wiring length of each internal IO bus. One side and the other side of different banks allocated to the bonding pads on one side / other side on the semiconductor chip are connected by corresponding internal IO buses.

[0010] Further, on the semiconductor chip, the bonding pads are arranged substantially on the center line of the semiconductor chip.
In addition, the semiconductor chip is arranged on one side or the other side of the semiconductor chip, and the memory mats are arranged on both sides of the bonding pad.

In particular, semiconductor memory devices tend to be synchronous SDRAMs composed of a plurality of banks, for example, four banks, eight banks, and more banks, and 64 Mbits, 256 Mbits, and even more bits. Some S
This is applied to a DRAM or the like. Also,
It goes without saying that the present invention can be applied to other semiconductor memory devices such as a DRAM.

Therefore, according to the semiconductor memory device including the SDRAM as described above, IO allocation of the memory mat is performed according to the arrangement of the bonding pads.
Variations in the wiring length of the internal IO bus connecting the bonding pad and the IO line of the corresponding memory mat can be eliminated, and the variation in the internal IO bus length can be reduced.

In particular, one side / other side of the bonding pad is allocated corresponding to one side / other side of the memory mat, respectively, and one side / other side of different banks allocated to one side / other side bonding pad. By connecting each with the corresponding internal IO bus,
Since no extra wiring is required, the wiring load can be minimized.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 1 is a configuration diagram showing a semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a layout diagram showing a semiconductor chip in the semiconductor memory device according to this embodiment, and FIG.
FIG. 4 is a layout diagram showing a bank in detail, and FIG. 4 is a layout diagram showing IO allocation of a memory mat in consideration of an internal IO bus.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device according to the present embodiment is, for example, a semiconductor memory device having a TSOP structure with a 54-pin LOC, and a 64-Mbit SDRAM composed of four banks.
And a lead frame 4 connected to the bonding pads 2 on the semiconductor chip 1 via wires 3. A connection portion between the semiconductor chip 1 and the lead frame 4 is formed of a sealing resin. The external terminals 6 are molded in a gull-wing shape from the side surfaces thereof.

In this semiconductor memory device, address terminals A0 to A13 for inputting an address signal are provided as external terminals 6.
Data input / output terminals DQ0 to DQ15 for data input / output,
Control signal terminals for inputting various control signals CLK, CKE, /
CS, / RAS, / CAS, / WE, DQML, DQM
U, power supply terminals Vcc, Vss, V for supplying various power supply voltages
ccq, Vssq, Vref and the like are provided.

These external terminals 6 are formed by cutting and molding the outer leads at one end of the lead frame 4 after molding with the sealing resin 5. On the other hand, the inner lead at the other end of the lead frame 4 is connected to the bonding pad 2 on the semiconductor chip 1 via the wire 3 before molding, and the external terminal 6 and the bonding pad 2 on the semiconductor chip 1 are electrically connected. And further connected to an internal circuit of the semiconductor chip 1 described later.

The semiconductor chip 1 includes, for example, as shown in FIG. 2, a memory mat including four banks Bank0 to Bank3, and its peripheral circuits. The banks Bank0 to Bank3 are divided into left and right sides in the row direction (horizontal direction) and upper and lower sides in the column direction (vertical direction), and are further divided into left and right sides in the row direction, respectively. Word driver M
They are arranged in pairs across the WD.

At the center of the banks Bank0 to Bank3 arranged on the upper and lower sides of the semiconductor chip 1, column decoders YDEC corresponding to the respective banks Bank0 to Bank3 are arranged. Further, on the center side, peripheral circuits such as a main amplifier MA, a data input / output circuit including a selector SLA and a buffer B, a timing generation circuit, and the like, and a bonding pad 2 for external connection shown in FIG. 1 are provided. ing.

In each of banks Bank0 to Bank3, for example, as shown in FIG. 3 (illustrating the left side of bank Bank0 as an example), a memory cell MC and a sense amplifier SA are arranged in the column direction of memory cell MC. A sub-word driver SWD is arranged in the row direction, and an FX driver, a control circuit for the sense amplifier SA, and the like are also arranged in an intersection area between the sense amplifier SA and the sub-word driver SWD.

In the banks Bank0 to Bank3, the main word line MWL by the main word driver MWD and the sub word line SWL by the sub word driver SWD are arranged so as to run in the row direction of the memory cells MC, and the column by the column decoder YDEC. The selection line YS and the bit line BL formed by the sense amplifier SA are arranged to run in the column direction of the memory cells MC.

Data can be read / written from / to the memory cell MC by specifying a row direction address by the main word line MWL and the sub word line SWL, and by specifying a column direction address by the column selection line YS and the bit line BL. Memory cells MC are selected,
Data is read from the memory cell MC to the main amplifier MA via the local IO line LIO and the main IO line MIO, while data is written via a write circuit.

The internal circuit of the semiconductor chip 1 is controlled based on a control signal input from the external terminal 6 of the semiconductor memory device via the bonding pad 2.
The commands such as bank active, read, write, precharge, and refresh, and internal control signals are generated by a timing generation circuit, which is a peripheral circuit of the device, and the operation of the internal circuit is controlled by the commands and the internal control signals. I have.

Next, regarding the operation of the present embodiment, an outline of the operation of the SDRAM will be briefly described first. Note that the operation of the SDRAM is different from that of a general-purpose DRAM controlled by rising / falling of various control signals in that the operation is controlled by a command defined by a combination of these control signals.

All operations of the SDRAM are performed in synchronization with the clock signal CLK, and each operation is controlled by a command. This command includes a chip select signal / CS and a column address strobe signal / CA
S, a row address strobe signal / RAS, and a write enable signal / WE are defined by a combination of control signals.

That is, High / Low of these control signals at the rising edge of the clock signal CLK.
, Various commands such as bank active, read, write, precharge, and refresh are defined, and these commands are decoded to make each circuit execute an operation corresponding to the command.

For example, in a standby state of a read operation or a write operation, a bank is selected by a setting of a bank active command to activate a specified word line, and when a read command is set, a bank is activated from a selected bank. Data can be read, and in the setting of a write command, data can be written to the selected bank.

Further, when a precharge command is set, a precharge operation of a designated bank can be executed. In this precharge, a precharge operation is automatically performed after a read operation or a write operation is completed. There are a read command with auto precharge and a write command with auto precharge to be executed.

Further, the refresh command includes, for example, an auto-refresh command and a self-refresh command. In setting the auto-refresh command, an address is generated internally and a refresh operation is automatically performed. This is performed for battery backup and the like, and after the self-refresh operation is completed, an auto-refresh operation is performed.

As described above, the bank active operation, read operation, write operation, precharge operation, refresh operation and the like of the SDRAM are executed. These operations are executed by, for example, starting the actual operation after precharging all the banks, setting the mode register, and performing auto-refresh after the power is turned on.

Next, IO allocation of a memory mat in consideration of an internal IO bus, which is a feature of the present invention, will be described with reference to the layout diagram of FIG.

For example, when the arrangement of the external terminals 6 of the semiconductor memory device is determined in advance as described above, the inner leads connected to the bonding pads 2 of the semiconductor chip 1 from the outer leads serving as the external terminals 6 of the lead frame 4. The arrangement of the bonding pads 2 on the semiconductor chip 1 is determined in accordance with the arrangement of the external terminals 6 so as to be substantially equal in consideration of the delay due to the length to the lead, the length of the wire 3 and the like.

That is, since the data input / output terminals DQ0 to DQ15 for data input / output are provided on the upper left and right sides in FIG.
The bonding pads 2 of the semiconductor chip 1 are arranged collectively on one side on the upper side (the right side in FIG. 4) together with the arrangement of Q15. In FIG. 4, the arrangement of the bonding pads 2 is 0, F (15), 1, E (14), 2,
D (13), 3, C (12), 4, B (11), 5, A
(10), 6, 9, 7, 8 are arranged in this order.

Each of the internal IO buses IO connecting the bonding pads 2 to the IO lines of the corresponding banks Bank0 to Bank3 via the main amplifier MA, etc.
IO of the memory mat so as to equalize the wiring length of the bus
Make the assignment.

Further, these internal IO buses IObus
0, F, 1, E, 2, D, 3, C of the bonding pad 2 on one side are set to the bank Ba so that the wiring length of
nk0-Bank3 into two divided IO lines,
4, B, 5, A, 6, of the other bonding pad 2
The numbers 9, 7, and 8 are assigned to the IO lines on the other side of the banks Bank0 to Bank3, respectively.

Then, one of the two banks Ba
IO lines nk0 to Bank3, bank Ba on the other side
The IO lines of nk0 to Bank3 are connected to the corresponding internal IO bus IObus via the main amplifier MA or the like.

For example, in FIG.
0, the right bank Bank0 divided into two
Then, from the right end, 0, F, 1, E, 2, D, 3, C (0
To IO), IO allocation is performed in the order of
At k0, 4, B, 5, A, 6, 9, 7, 8 from the right end
IO allocation is performed in the order of (4 to 8).

Similarly, with respect to the banks Bank1 to Bank3, the right banks Bank1 to Bank3 are arranged in the order of 0 to C from the right end in order from the left bank Bank1 to Bank3.
In nk3, IO allocation is performed in the order of 4 to 8 from the right end.

Further, regarding the internal IO bus IObus,
In the upper banks Bank0 and Bank2, 0 to C of the right divided bank Bank0 on the right are divided into two adjacent banks on the right side.
The divided IO banks are connected by an internal IO bus IObus corresponding to 0 to C of the right bank Bank2, and 4 to 8 of the left bank Bank0 are connected to the left bank Bank0.
Internal IO bus IObus corresponding to 4 to 8 of 2, respectively
Connect with

Similarly, the lower banks Bank1, Bank
Regarding k3, 0-C of the right bank Bank1 is replaced by 0-C of the right bank Bank3,
4 to 8 of k1 correspond to 4 to 8 of the left bank Bank3, respectively, and are connected by the internal IO bus IObus.

The upper banks Bank0 and Bank
Also between 2 and the lower banks Bank1 and Bank3, the corresponding 0-F are connected by wiring. At this time, the upper bank Bank0 and the lower bank Bank1 are directly connected, and the upper bank Bank2 and the lower bank Bank3 are connected via the bonding pad 2.

Therefore, according to the semiconductor memory device of the present embodiment, 0 to C / 4 of banks Bank0 to Bank3 are adjusted in accordance with the arrangement of 0 to C / 4 to 8 of bonding pads 2.
~ 8 IO allocation, Bank0 and Bank0
By connecting 0 / C / 4 to 8 of k2 / Bank1 and Bank3 by using the internal IO bus IObus in correspondence with each other, the variation in the wiring length of the internal IO bus IObus can be reduced, and no extra wiring is required. Therefore, the wiring load can be minimized. As a result, access can be speeded up.

Further, the four banks Bank as described above are used.
In the semiconductor memory device composed of 0 to Bank3, the internal I / O bus IOb is allocated by allocating the memory mats in consideration of the internal IO bus IObus.
us with approximately the same wiring length and about 1
/ 2 length.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 5
Although the description has been made with reference to the example of the semiconductor memory device having the TSOP structure using the 4-pin LOC, the present invention is not limited to this.
The present invention can be applied to a larger number of pins such as 80 pins, a smaller number of pins such as 40 pins, and other package structures such as SOP and SOJ. Deformation is possible.

A 64-Mbit S consisting of 4 banks
Although the description has been made with reference to the example of a DRAM, an SDRAM which has a tendency to increase the number of banks to 8 banks or more, and 256 Mbits or more bits is also widely applicable. With the configuration, the effect of the present invention is further increased.

In the above description, the invention made mainly by the present inventor is described in the technical field to which the invention belongs.
Of the present invention has been described, but the present invention is not limited to this.
AM, RAM, ROM, PROM, EPROM, EEP
The present invention is widely applicable to other semiconductor memory devices, such as ROMs, which require memory mat IO allocation.

[0050]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) By allocating the IOs of the memory mats in accordance with the arrangement of the bonding pads, the variation in the wiring length of the internal IO bus connecting the bonding pads and the IO lines of the corresponding memory mats can be eliminated. It is possible to reduce the variation in the internal IO bus length.

(2) One side / other side of the bonding pad is assigned to correspond to one side / the other side of the memory mat, respectively. By connecting the other side with the corresponding internal IO bus, no extra wiring is required, so that the wiring load on the internal IO bus can be minimized.

(3) According to the above (1) and (2), SDRAM, D
In a semiconductor memory device such as a RAM, by considering the arrangement of internal IO buses in IO allocation of a memory mat,
Since the wiring length of the internal IO bus can be made uniform and minimized, high-speed access can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a layout diagram showing a semiconductor chip in the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a layout diagram showing a bank in detail in the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is a layout diagram showing IO allocation of a memory mat in consideration of an internal IO bus in the semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 2 bonding pad 3 wire 4 lead frame 5 sealing resin 6 external terminal Bank0 to Bank3 bank MWD main word driver YDEC column decoder MA main amplifier SLA selector B buffer MC memory cell SA sense amplifier SWD subword driver MWL main word line SWL Sub word line YS Column select line BL Bit line LIO Local IO line MIO Main IO line IObus Internal IO bus

Claims (5)

[Claims] 1. A semiconductor memory device comprising: a semiconductor chip having a memory mat and a peripheral circuit formed thereon; and a lead frame having one end connected to a bonding pad of the semiconductor chip and the other end serving as an external terminal. The arrangement of each bonding pad on the semiconductor chip is determined according to the arrangement of each external terminal of the lead frame, and each bonding pad and the IO line of the corresponding memory mat are determined according to the arrangement of these bonding pads. A semiconductor memory device, wherein IO allocation of said memory mat is performed so as to equalize the wiring length of each connected internal IO bus. 2. The semiconductor memory device according to claim 1, wherein IO allocation of said memory mat is performed by each of said internal I / Os.
One bonding pad on the semiconductor chip corresponds to one side of the memory mat, and the other bonding pad on the semiconductor chip corresponds to the other side of the memory mat, so that the wiring length of the O bus is minimized. A semiconductor memory device characterized by being assigned. 3. The semiconductor memory device according to claim 2, wherein said memory mat comprises a plurality of banks.
The internal IOs correspond to one side of different banks allocated to one bonding pad on the semiconductor chip and the other side of different banks allocated to the other bonding pad on the semiconductor chip, respectively.
A semiconductor memory device connected by a bus. 4. The semiconductor memory device according to claim 1, wherein on said semiconductor chip, said bonding pad is arranged substantially on a center line of said semiconductor chip, and on one side or the other side of said semiconductor chip. The semiconductor memory device is arranged on one side, and the memory mats are arranged on both sides of the bonding pad. 5. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a synchronous synchronous DRAM comprising a plurality of banks. .