JPH1196784A - Read only memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by reducing drain capacity of a memory cell connected to a bit line. SOLUTION: Regarding plural memory cell, a representative memory cell 8 representing plural memory cells 1 is provided. Data of the memory cell 1 connected to a word line 2 selected by an address decoder 4 is read out to a bit line 3 through a sub-bit line 7 and the representative memory cell 8. Also, discharge of the sub-bit line 7 is performed by a transistor 9 for discharge based on control of a control circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a read-only memory with reduced power consumption.

[0002]

2. Description of the Related Art FIG. 6 is a diagram showing a conventional read-only memory of a precharge type, in which 1 is a memory cell, 2 is a word line, 3 is a bit line, 4 is an address decoder, and 5 is an address signal. , 6 are word line enable signals. In this read-only memory, a plurality of word lines 2 are arranged, a plurality of bit lines 3 are arranged orthogonal to the word lines 2, and a memory cell 1 is arranged at each intersection of the word lines 2 and the bit lines 3 to form a memory cell array. ing. A plurality of address decoders 4 are provided for this memory cell array, and address signals 5 are decoded by these address decoders 4, and a specific word line 2 is selected and driven.

A memory cell 1 to be read is selected from a plurality of specific word lines 2 and specific bit lines 3.
Is performed by selecting. The memory cell 1 is formed of an N-channel transistor, and one end of the N-channel transistor is connected to the ground potential (= “L”). In this configuration example, memory cell 1 corresponding to data "1"
The other end of the channel transistor is connected to the bit line 3, and the memory cell 1 corresponding to data “0” is open without connecting the other end of the N-channel transistor to the bit line 3. Contrary to this configuration, it is also possible to adopt a configuration in which connection is not made to the bit line 3 when data is “1” and connection is made when data is “0”.

Next, the operation will be described. When reading data, first, the potential of the bit line 3 is precharged to the “H” level. Then, the address decoder 4 decodes the address signal 5. Only one word line 2 receiving the output signal of the address decoder 4 is selected from all the word lines. During the precharge, the word line enable signal 6 is at the “L” level, and even after the selection of the word line 2 is completed, the word lines 2 are all at the “L” level. This is to prevent the discharge of the bit line 3 from the memory cell 1 during the precharge.

After the completion of the precharge, reading of the memory cell 1 is started. When the word line enable signal 6 changes from the “L” level to the “H” level, only the word line 2 selected by the address decoder 4 changes from the “L” level to the “H” level. Accordingly, the N-channel transistor of the memory cell 1 connected to the selected word line 2 is turned on.

When the memory cell 1 in the “ON” state is connected to the bit line 3, that is, when the memory cell 1 corresponds to data “1”, the charge charged through the memory cell 1 is extracted and the bit line 3 is discharged. 3 is finally ground potential (=
"L").

When the memory cell 1 in the "ON" state is not connected to the bit line 3, that is, the data "0"
, The charged charge is not extracted, and the potential of the bit line 3 is maintained at the “H” level.
The potential of the bit line 3 becomes “L” level or “H”.
Whether the data to be read is "1" or "0" is determined depending on whether the level is held.

[0008]

Here, the power required to charge the bit line 3 will be considered. The power required for charging is proportional to the capacity of the bit line 3. Although there is a difference depending on the manufacturing method, the drain capacitance of the N-channel transistor of the memory cell 1 connected to the bit line 3 may be several times larger than the wiring capacitance of the bit line 3. Since the conventional read-only memory is configured as described above, there is a problem that when there are many memory cells 1 corresponding to data "1", the power consumed for precharging the bit line 3 is large.

Another conventional technique is disclosed in Japanese Unexamined Patent Publication No.
There is one disclosed in US Pat. No. 15,595. This is a technology in which memory cells connected to the bit lines are reduced and data is read at high speed by dividing the bit lines and performing column selection in a plurality of stages, but the problem is that the overall power consumption is similarly large. was there.

The present invention has been made to solve the above problems, and reduces power consumption by reducing the drain capacitance of the N-channel transistor of the memory cell 1 connected to the bit line 3. It is intended to obtain a read-only memory.

[0011]

A read-only memory according to the present invention is connected to a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, and each of the word lines, and specifies an address. And a plurality of address decoders that receive the address signal to be selected and select the word line, and are arranged corresponding to intersections of the word line and the bit line, connected to the respective word lines, and programmed. A plurality of memory cells holding data, and a first semiconductor element for outputting data held by a predetermined number of the memory cells arranged along the bit line to the bit line via a sub-bit line; A second semiconductor element for discharging the sub-bit line, and control means for controlling the discharge performed by the second semiconductor element. Before reading the data held by the memory cell, the bit line is precharged, and the sub-bit line is discharged by the second semiconductor element under the control of the control means. In the case of reading, the control means stops the discharge of the sub-bit line, and transfers the data held by the memory cell connected to the word line selected by the address decoder to the sub-bit line and the first semiconductor element. Through the bit line.

A read-only memory according to the present invention does not connect a first semiconductor element to the bit line in accordance with data content held by a predetermined number of memory cells arranged along a bit line. It is.

In a read-only memory according to the present invention, an address decoder receives an address signal specifying an upper address and an lower address driven by the upper address decoder. A predetermined number of memory cells arranged along a bit line and connected to each word line connected to a lower address decoder driven by the same upper address decoder; When reading the data held by the sub-bit line, the discharge of the sub-bit line is stopped based on the output of the upper address decoder.

In a read-only memory according to the present invention, a predetermined number of memory cell groups arranged along a bit line are made into one group, and control means of two groups adjacent in the bit line direction is shared. Things.

The read-only memory according to the present invention comprises a word line switching detecting means for detecting whether or not word line switching has occurred. When reading data held in a memory cell continuously, the word line switching detecting means is used. Does not detect the switching of the word line, the control means does not discharge the sub-bit line.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. In FIG. 1, 1 is a memory cell, 2 is a word line, 3 is a bit line, 4 is an address decoder, 5 is an address signal, and 6 is a word line enable signal, which is equivalent to FIG. . 7 is a sub-bit line, 8 is a representative memory cell (first semiconductor element), 9 is a discharge transistor (second semiconductor element), and 10 is a control circuit (control means) of the discharge transistor 9.

The read-only memory according to this embodiment has a plurality of word lines 2 arranged, and a plurality of bit lines 3 arranged so as to intersect (generally orthogonal) with the word lines 2, and the word lines 2 intersect with the bit lines 3. One memory cell 1 is indirectly arranged for each point via a representative memory cell 8 to form a memory cell array. A plurality of address decoders 4 are provided for this memory cell array,
The word line 2 is selected and driven by the address decoder 4.

As shown in FIG. 1, a predetermined number of memory cells 1 arranged along a plurality of continuous word lines 2 are grouped together, and all memory cells are divided into a plurality of groups. The number of groups to be divided is set to an appropriate value according to the total number of memory cells and the lengths of bit lines and sub-bit lines. A plurality of bit lines 3 intersecting with word lines 2
Are divided by this group. Here, consider one specific bit line 3 in one group. The number of memory cells 1 arranged along one bit line 3 in the divided group is n (n = 4 in FIG. 1).
Number. One sub-bit line 7, one representative memory cell 8, and one discharge transistor 9 are provided for each of the n memory cells 1.

The representative memory cell 8 is an Nch transistor, the drain of which is connected to the bit line 3, the gate of which is connected to the sub-bit line 7, and the source of which is connected to the ground potential (= "L").
The discharge transistor 9 is an Nch transistor, the drain of which is connected to the sub-bit line 7, the source of which is connected to the ground potential (= “L”), and a control circuit 10 for the discharge transistor 9 is provided. To the gate of the transistor 9 for use.

Next, a method of connecting the memory cells 1 will be described. The n memory cells 1 include a word line 2 and a bit line 3
The gates of these memory cells 1 are connected to the corresponding word lines 2, respectively. Regarding the drains of the n memory cells 1, the memory cell 1 corresponding to data "1" is connected to the sub-bit line 7, and the memory cell 1 corresponding to data "0" is not connected to the sub-bit line 7, Open. And
The sources of all n memory cells 1 are connected to the power supply potential (=
"H"). Therefore, the memory cell 1 is connected to the sub bit line 7 but not directly to the bit line 3.

In the above description, one bit line 3 in an area defined by one group is described.
In a similar manner, for each bit line 3 of all defined groups in the memory, a memory cell 1 and a sub-bit line 7
, Representative memory cell 8 and discharge transistor 9
Make the connection.

Contrary to this embodiment, the drain of the memory cell 1 corresponding to data "1" is not connected to the sub bit line 7, and the drain of the memory cell 1 corresponding to data "0" is connected to the sub bit line. 7 can be configured.

Next, the operation will be described. When data is not read, the word lines 2 are all at the “L” level, but the output signal of the control circuit 10 connected to the gate of the discharge transistor 9 is set at the “H” level, The potential is kept at "L" level. This is because the gate of the representative memory cell 8 is closed during the precharge performed when reading data, and the discharge of the bit line 3 is prevented.

When reading data, first, the potential of the bit line 3 is precharged to the "H" level. Then, the address decoder 4 decodes the address signal 5.
According to the decoding result of the address decoder 4, the word line 2
Is selected only from among all. During the precharge, the word line enable signal 6 is at the “L” level, and even after the selection of the word line 2 is completed, the word lines 2 are all at the “L” level. This is to prevent the bit line 3 from being discharged by the memory cell 1 and the representative memory cell 8 during the precharge.

Next, the output signal of the control circuit 10 is set to "L" level, and the discharge transistor is set to "OF".
F "state, and the sub-bit line 7 is set to the ground potential (=" L ").
And separate. After the precharge of the bit line 3 is completed, the word line enable signal 6 is changed from “L” level to “H” level, so that the selected word line 2 also changes from “L” level to “H” level. Accordingly, the N-channel transistor of the memory cell 1 connected to the selected word line 2 is turned on.

When the memory cell 1 in the “ON” state is connected to the sub-bit line 7, that is, when the memory cell 1 corresponds to data “1”, the sub-bit line 7 is charged via the memory cell 1. As a result, the representative memory cell 8 is turned “ON”.
State, and the bit line 3
Is extracted, and the potential of the bit line 3 finally becomes the ground potential (= “L”).

On the other hand, when the memory cell 1 in the "ON" state is not connected to the sub-bit line 7, that is, when it corresponds to data "0", the sub-bit line 7 is not charged. Therefore, since the representative memory cell 8 remains in the "OFF" state, the charged charge is not extracted, and the potential of the bit line 3 is maintained at the "H" level.

Here, the power required to charge one bit line 3 will be considered. The power required for charging is proportional to the capacity of the bit line 3. The capacity of the bit line 3 is a value obtained by adding the wiring capacity and the total drain capacity of the memory cells connected to the bit line 3. In the case of this embodiment, the memory cells connected to the bit line 3 are not the memory cells 1 but the representative memory cells 8, and the number thereof is smaller than the number of the memory cells 1. The number of memory cells 1 arranged on one bit line 3 in the divided group is n, and the total number of memory cells 1 along one bit line 3 in all groups is m. Then, the number of representative memory cells 8 connected to one bit line 3 becomes m / n. In the related art, since a maximum of m memory cells 1 are connected to the bit line 3, the number of memory cells is reduced to 1 / n in this embodiment.

In this embodiment, the memory cell 1 connected to the selected word line 2 is also turned on when reading out the memory cell 1 after the bit line 3 is precharged. Since the sub-bit line 7 along the line 3 is also charged, the power consumption of the sub-bit line 7 needs to be considered as the power required for reading, but the memory cell 1 connected to the word line selected by the address decoder 4 In addition, since only the sub-bit line 7 connected to the memory cell 1 in which the data is "1" needs to be charged, the power required as a whole is greatly reduced as compared with the related art.

In this embodiment, the number of memory cells 1 in each group is the same n, but this number may be different for each group.

As described above, according to the first embodiment, in the read-only memory, a representative memory cell representing a plurality of memory cells, a transistor for discharging the gate of the representative memory cell, and the transistor Is provided, the number of memory cells connected to the bit line can be reduced, the capacity of the bit line can be reduced, and power consumption can be reduced.

Embodiment 2 FIG. In FIG. 2, 1 is a memory cell, 2 is a word line, 3 is a bit line, 4 is an address decoder, 5 is an address signal, 6 is a word line enable signal, 7 is a sub-bit line, 8 is a representative memory cell, and 9 is discharge. A transistor l0 is a control circuit for the discharge transistor 9, which is equivalent to that of the first embodiment shown in FIG.

The configuration of the read-only memory of this embodiment is similar to that of the first embodiment in that all the memory cells are divided into a plurality of groups, and each of the bit lines 3 in each group is connected to the sub-bit line 7 and The connection is performed by providing one representative memory cell 8 and one discharge transistor 9. Also, the control circuit 10 is provided similarly to the first embodiment,
Connected to the discharge transistor 9. further,
The connection method of the memory cell 1 is the same as that of the first embodiment.

The difference between this embodiment and the first embodiment is that the connection method of the drain of the representative memory cell 8 is different. The source of the representative memory cell 8 is connected to the ground potential (=
(L), the gate is connected to the sub-bit line 7 as in the first embodiment, but in the first embodiment,
The drain of the representative memory cell 8 was connected to the bit line 3 unconditionally. However, when there is no connection between the sub-bit line 7 and the memory cell 1, the representative memory cell 8 does not turn "ON". Therefore, in the first embodiment, by connecting the drain of the representative memory cell 8 and the bit line 3, the capacity of the bit line 3 is increased wastefully.

Therefore, in order to reduce the capacity of the useless bit line 3, if there is no connection of the memory cell 1 in each sub bit line 7, the sub bit line 7
Is connected to the gate, and the drain of the representative memory cell 8 is opened without being connected to the corresponding bit line 3. In each sub bit line 7, the memory cell 1
When there is one or more connections, the drain of the representative memory cell 8 whose sub-bit line 7 is connected to the gate is connected to the corresponding bit line 3 as in the first embodiment.

Next, the operation will be described. The operation is also the same as that of the first embodiment. When data is not read, the output signal of the control circuit 10 is set to “H” level.
The potential of the sub bit line 7 is kept at the "L" level. When reading data, first, the bit line 3 is precharged, the address decoder 4 decodes the address signal 5, and selects only one of all the word lines 2. Next, the output signal of the control circuit 10 is set to “L” level. Then, for reading after completion of the precharge, the word line enable signal 6 is changed from “L” level to “H” level, and the N-channel transistor of the memory cell 1 connected to the selected word line 2 is turned “ON”. State. After that, the change in the level of the bit line 3 is read.

When the memory cell 1 in the "ON" state is connected to the sub-bit line 7, the representative memory cell 8 and the bit line 3 are connected at this time.
, The sub-bit line 7 is charged, the representative memory cell 8 is turned on, and the charge charged in the bit line 3 through the representative memory cell 8 is extracted.
The potential of the bit line 3 finally becomes the ground potential (= "L").

On the other hand, when the memory cell 1 in the "ON" state is not connected to the sub bit line 7, the sub bit line 7 is not charged, and the representative memory cell 8 is set to "OF".
Since the state remains in the "F" state, the charged charge is not extracted, and the potential of the bit line 3 is maintained at the "H" level. When 1 is not connected, since the drain of the representative memory cell 8 whose sub-bit line 7 is connected to the gate is not connected to the bit line 3, the charge of the bit line 3 is extracted in the representative memory cell 8. Therefore, the potential of the bit line 3 is maintained at the “H” level.

Here, the power required to charge one bit line 3 will be considered. The power required for charging is, as described in the first embodiment, the bit line 3
The capacitance of the bit line 3 is a value obtained by adding the wiring capacitance and the total amount of the drain capacitances of the memory cells connected to the bit line 3. In the case of this embodiment,
The memory cell connected to the bit line 3 is a representative memory cell 8
In addition, since the representative memory cell 8 corresponding to only the memory cell 1 that cannot be turned on is not connected to the bit line 3, it is smaller than the first embodiment and one bit line 3 Is less than m / n.

In this embodiment, as in the first embodiment, the sub-bit line along the bit line 3 is also charged at the time of reading data from the memory cell 1.
However, as described in the first embodiment, the power required as a whole is greatly reduced as compared with the conventional case.

In this embodiment, the number of memory cells 1 in each group is the same n, but this number may be different for each group.

As described above, according to the second embodiment, the connection between the representative memory cell and the bit line is not performed under specific conditions, thereby further reducing the number of memory cells connected to the bit line. Thus, the capacity of the memory cell connected to the bit line can be reduced as compared with the first embodiment, and an effect that power consumption can be reduced can be obtained.

Embodiment 3 In FIG. 3, 1 is a memory cell, 2 is a word line, 3 is a bit line, 4a is an upper address decoder, 4b is a lower address decoder, 5a is an upper address signal, 5b is a lower address signal, 6 is a word line enable signal, 7 is a sub-bit line, 8 is a representative memory cell, 9 is a discharge transistor, and 10 is a control circuit of the discharge transistor 9. The input signal of the control circuit 10 uses the output signal of the upper address decoder 4a. In this embodiment, a NAND operation circuit is employed for the control circuit 10, but the control circuit can be configured with other circuits. Here, the upper address signal 5a and the lower address signal 5b are obtained by dividing the address signal input to the memory into upper and lower addresses.

The read-only memory of this embodiment is
A plurality of word lines 2 are arranged, and a plurality of bit lines 3 are arranged so as to intersect the word lines 2. One memory cell 1 is arranged at each intersection of the word lines 2 and the bit lines 3 to form a memory cell array. I have. A plurality of upper address decoders 4a are provided for this memory cell array, and the word line 2 is selected and driven by a lower address decoder 4b that inputs an output signal of the upper address decoder 4a. Here, all the memory cells 1 driven by the output signal of one upper address decoder 4a and arranged along the plurality of word lines 2 are grouped into one group, and all the memory cells are divided into a plurality of groups.

The plurality of bit lines 3 intersecting the word lines 2 are divided by this group. Here, consider one specific bit line 3 in one group.
The number of memory cells 1 arranged along one bit line 3 in the divided group is assumed to be n. One sub-bit line 7, one representative memory cell 8, and one discharge transistor 9 are provided for each of the n memory cells 1. The representative memory cell 8 is an Nch transistor, the drain of which is connected to the bit line 3, the gate of which is connected to the sub-bit line 7, and the source of which is connected to the ground potential (= “L”).

The discharge transistor 9 is an Nch transistor, and its drain is connected to the sub-bit line 7.
The source is connected to the ground potential (= “L”), and a control circuit 10 for the discharge transistor 9 is provided. The input of the control circuit 10 uses the output signal of the upper address decoder 4a. The output of 10 is connected to the gate of the discharging transistor 9. In this embodiment, the discharge of the sub-bit line can be stopped only for the group selected by the output signal of the upper address decoder by using the output signal of the upper address decoder 4a.

In this embodiment, the control circuit 10 is a circuit for performing a NAND operation of the word line enable signal 6 and the output signal of the upper address decoder 4a, and always discharges when the word line enable signal 6 is at "L" level. The transistor 9 is turned on. As described above, by using the output signal of the upper address decoder 4a, the control circuit 10 can be configured with a simple circuit.
Note that the memory cell 1 and the sub-bit line 7
Is the same as in the first embodiment.

Next, the operation will be described. When data is not read, the word line enable signal 6 is at the "L" level, so that the output signal of the control circuit 10 composed of NAND connected to the gate of the discharge transistor 9 is kept at the "H" level. I have. As a result, the potential of sub-bit line 7 is maintained at the "L" level. When reading data, first, the potential of the bit line 3 is precharged to the “H” level. Then, the upper address decoder 4a decodes the upper address signal 5a, and the lower address decoder 4b decodes the lower address signal 5b.

The lower address decoder 4b is selected in response to the output signal of the upper address decoder 4a, and only one word line 2 is selected from all the word lines 2 according to the decoding result of the lower address decoder 4b. During the precharge, the word line enable signal 6 is “L”.
Level, and all the word lines 2 are at the “L” level even after the selection of the word line 2 is completed. This is to prevent the bit line 3 from being discharged by the memory cell 1 and the representative memory cell 8 during the precharge.

After completion of the precharge, reading is started. By changing the word line enable signal 6 from “L” level to “H” level, the selected word line 2 also changes from “L” level to “H” level. Accordingly, the memory cell 1 connected to the selected word line 2
Are turned on. Since the word line enable signal 6 has become "H" level, the output of the control circuit 10 becomes "L" level. As a result, the discharge transistors in the region defined by the above group are turned off, and the sub-bit line 7 is separated from the ground potential (= “L”).

When the memory cell 1 in the “ON” state is connected to the sub bit line 7, that is, when the memory cell 1 corresponds to data “1”, the sub bit line 7 is charged via the memory cell 1. As a result, the representative memory cell 8 is turned “ON”.
State, and the bit line 3
Is extracted, and the potential of the bit line 3 finally becomes the ground potential (= “L”).

On the other hand, when the memory cell 1 in the "ON" state is not connected to the sub bit line 7, that is, when the memory cell 1 corresponds to data "0", the sub bit line 7 is not charged. Therefore, since the representative memory cell 8 remains in the "OFF" state, the charged charge is not extracted, and the potential of the bit line 3 is maintained at the "H" level.

In the first and second embodiments,
While the discharge of all the discharge transistors 9 is stopped when data is read, in the third embodiment, as described above, only the discharge transistors of the group selected by the output signal of the upper address decoder are used. 9 discharge has been stopped.

As described above, according to the third embodiment, the input signal of the control circuit of the discharge transistor 9 is selected by the output signal of the upper address decoder by using the output signal of the upper address decoder. Only the group can stop the discharge of the sub-bit line. Therefore, in addition to the effect obtained in the first embodiment, an effect that power consumption can be reduced as compared with the case where the discharge of all the sub-bit lines is stopped in one read operation is obtained. Further, since the output signal of the upper address decoder is used, an effect that addition of hardware constituting the control circuit can be reduced can be obtained.

Embodiment 4 In FIG. 4, 1 is a memory cell, 2 is a word line, 3 is a bit line, 4 is an address decoder, 5 is an address signal, 6 is a word line enable signal, 7 is a sub-bit line, 8 is a representative memory cell, and 9 is discharge. A transistor l0 is a control circuit for the discharge transistor 9.

As in the first embodiment, the configuration of the read-only memory in this embodiment is such that all memory cells are divided into a plurality of groups, and each of the bit lines 3 in each group is Representative memory cell 8
And the discharge transistors 9 are provided one by one to make connection. The control circuit 10 is also provided in the same manner as in the first embodiment, and is connected to the discharge transistor 9. The connection method of the memory cells 1 is the same as that of the first embodiment.

The difference between this embodiment and the first embodiment is that the control signals for the discharge transistors 9 of two adjacent groups are shared. That is,
The control of the discharge transistors 9 in two adjacent groups is performed by the same control circuit 10. By performing this for all the groups, it is possible to reduce the number of signal lines of control signals input to the discharge transistors 9 by half.

By sharing the control signals, the memory cells 1 in two adjacent groups are
, The discharge transistor 9 is turned “ON” to discharge the sub-bit lines 7 belonging to both groups. Also,
When the memory cell 1 in one of the two adjacent groups is specified by the address decoder 4, the discharge transistor 9 is turned off to stop discharging the sub-bit lines 7 belonging to both groups. In this case, the sub bit lines 7 belonging to both groups are discharged at the time of the previous data reading, and even during the reading of data from the sub bit lines 7 belonging to one group, the sub bit lines 7 belonging to the other group are also discharged. 7 does not cause any problem because the ground potential is maintained without discharging.

Next, the operation will be described. The operation is the same as that of the first embodiment. When data is not read, the output signal of control circuit 10 is set to "H" level, and the potentials of sub-bit lines 7 belonging to both groups are set to "L" level. To keep. When reading data, first, the bit line 3 is precharged, the address signal 5 is decoded, and only one of the word lines 2 is selected. Then, before starting reading, the output signal of the control circuit 10 is set to “L” level, and the discharge of the sub-bit lines 7 belonging to both groups is stopped. After the precharge is completed, the word line enable signal 6 is changed from "L" level to "H" level, and the N-channel transistor of the memory cell 1 connected to the selected word line 2 is turned on. Then, the level change of the bit line 3 is read.

When the memory cell 1 in the "ON" state is connected to the sub-bit line 7, the sub-bit line 7 is charged via the memory cell 1, so that the representative memory cell 8
Is turned on, the charge charged in the bit line 3 is extracted through the representative memory cell 8, and the potential of the bit line 3 finally becomes the ground potential (= "L"). On the other hand, when the memory cell 1 in the “ON” state is not connected to the sub-bit line 7, the sub-bit line 7 is not charged, and the representative memory cell 8 remains in the “OFF” state. Is not extracted, and the potential of the bit line 3 is maintained at the “H” level.

As described above, according to the fourth embodiment, in addition to the effects obtained in the first embodiment, the control signal for the discharge transistors existing in the adjacent groups is shared, so that the discharge is performed. The number of signal lines of the control signal input to the transistor for use can be halved. In addition, since the number of signal lines is halved, the number of times the signal lines are changed is also halved. As a result, the effect of reducing power consumption can be obtained.

Embodiment 5 In FIG. 5, 1 is a memory cell, 2 is a word line, 3 is a bit line, 4 is an address decoder, 5 is an address signal, 6 is a word line enable signal, 7 is a sub-bit line, 8 is a representative memory cell, and 9 is discharge. Transistor 10, a control circuit for the discharge transistor 9, and 11 a word line switching detection circuit (word line switching detection means). The input of the control circuit 10 uses the output of the word line switching detection circuit 11.

As in the first embodiment, the configuration of the read-only memory in this embodiment divides all the memory cells into a plurality of groups, and for each bit line 3 in each group, The connection is made by providing one memory cell 8 and one discharge transistor 9. Also, the connection method of the memory cell 1 is the same as that of the first embodiment.
Is the same as

Next, the control circuit 10 for the discharge transistor 9 will be considered. Here, the word line switching detection circuit 11 reads two consecutive data from the memory cell 1 connected to the same word line 2 or the memory cell 1 connected to a different word line 2 It is determined whether the process is performed from There is provided a control circuit 10 which receives the output signal of the word line switching detection circuit 11 as an input. The output signal of the control circuit 10 is used as a control signal of the discharge transistor 9. This control circuit 10
Receives the output signal of the word line switching detection circuit 11,
When continuous data reading is performed from the memory cell 1 connected to the same word line 2, the ground potential (=
"L") to prevent the sub-bit lines 7 in the group to which the word line belongs from being discharged.

Next, the operation will be described. First, consider one data read. The operation at this time is the same as that of the first embodiment. First, the bit line 3 is precharged, the address signal 5 is decoded, and only one of the word lines 2 is selected. Then, the output signal of the control circuit 10 is set to the “L” level before the start of reading, and the word line enable signal 6 is changed to the “L” level after the precharge is completed.
The N-channel transistor of the memory cell 1 connected to the selected word line 2 is changed to "H" level from the "H" level. Then, the level change of the bit line 3 is read.

When the memory cell 1 in the “ON” state is connected to the sub-bit line 7, the sub-bit line 7 is charged via the memory cell 1, so that the representative memory cell 8
Is turned on, the charge charged in the bit line 3 is extracted through the representative memory cell 8, and the potential of the bit line 3 finally becomes the ground potential (= "L").

On the other hand, when the memory cell 1 in the “ON” state is not connected to the sub bit line 7, the sub bit line 7 is not charged, and the representative memory cell 8 is “OFF”.
Since the state remains, the charged charge is not extracted, and the potential of the bit line 3 is maintained at the “H” level.

Next, consider a case where data is continuously read. First, in the case where continuous data reading is performed in the memory cells 1 connected to different word lines 2, the above-described operation at the time of one data reading is repeated at each reading, thereby reading data. Is performed.

On the other hand, when continuous data reading is performed in the memory cell 1 connected to the same word line 2, data reading is performed as follows. When one word line 2 is driven to read data once, not only the sub bit line 7 corresponding to the memory cell 1 from which data is read but also other sub bit lines 7 in the same group. The potential is charged or maintained by all the memory cells 1 connected to the driven word line 2. In other words, once data is read, the information of the memory cell 1 connected to the same word line 2 is all the corresponding sub bit line 7
Will be read out.

Therefore, when reading the next data, the word line switching detection circuit 11 detects that there is no word line switching, and the discharge transistor 9
Is set to the "OFF" state, the discharge of the sub-bit line 7 is stopped, and the potential of the sub-bit line 7 set at the time of the previous data reading is made available. In the continuous data reading, data of another memory cell 1 connected to the same word line 2 can be read by the retained potential of the sub bit line 7.

In this embodiment, the word line switching detection circuit 11 detects the presence / absence of the word line switching from the address signal, but may detect the presence / absence of the word line switching.

As described above, according to the fifth embodiment, in addition to the effect obtained in the first embodiment, whether continuous data reading is performed from the memory cells connected to the same word line Alternatively, by providing a word line switching detection circuit for determining whether the operation is performed from a memory cell connected to a different word line, the number of times of discharging the sub-bit line can be reduced, and the electric charge charged on the sub-bit line is not wasted. The effect of reducing power consumption can be obtained.

[0073]

As described above, according to the present invention, a representative memory cell representing a plurality of memory cells, a transistor for discharging the gate of the representative memory cell, and a transistor are provided in the read-only memory. By providing the control circuit, the number of memory cells connected to the bit line can be reduced, the capacity of the bit line can be reduced, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a read-only memory according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram showing a read-only memory according to a second embodiment of the present invention;

FIG. 3 is a configuration diagram showing a read-only memory according to Embodiment 3 of the present invention;

FIG. 4 is a configuration diagram showing a read-only memory according to a fourth embodiment of the present invention;

FIG. 5 is a configuration diagram showing a read-only memory according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram showing a conventional read-only memory.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 memory cell, 2 word lines, 3 bit lines, 4 address decoders, 4a upper address decoder, 4b lower address decoder, 5 address signals, 7 sub-bit lines, 8 representative memory cells (first semiconductor element), 9 discharge transistors (Second semiconductor element), 1
0 Control circuit (control means), 11 word line switching detecting circuit (word line switching detecting means).

Claims (5)

[Claims] A plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of bit lines connected to the respective word lines and receiving an address signal designating an address to select the word lines. An address decoder, a plurality of memory cells arranged corresponding to intersections of the word lines and the bit lines, connected to the respective word lines, and holding programmed data; and A first semiconductor element for outputting data held by a predetermined number of the memory cells arranged along the sub-bit line to the bit line, and a second semiconductor element for discharging the sub-bit line And control means for controlling the discharge performed by the second semiconductor element, wherein before reading the data held by the memory cell, In addition to precharging the bit line and discharging the sub-bit line by the second semiconductor element under the control of the control means, and reading out the data held in the memory cell, Stopping discharge of a line, and reading out data held by a memory cell connected to the word line selected by the address decoder to the bit line via the sub-bit line and the first semiconductor element. Read only memory. 2. The semiconductor device according to claim 1, wherein the first semiconductor element is not connected to the bit line in accordance with data contents held by a predetermined number of memory cells arranged along the bit line. Read only memory as described. 3. An address decoder, comprising: an upper address decoder receiving an address signal designating an upper address;
A predetermined number of memory cells arranged along a bit line are constituted by a lower address decoder which receives an address signal designating a lower address and is driven by the upper address decoder. When reading data held in the memory cell connected to each word line connected to the driven lower address decoder, discharging of the sub-bit line is stopped based on an output of the upper address decoder. Claim 1
Read only memory as described. 4. The method according to claim 1, wherein a predetermined number of memory cell groups arranged along the bit lines are grouped into one group, and control means for two groups adjacent in the bit line direction is shared. 2. The read-only memory according to 1. 5. A semiconductor memory device comprising: a word line switching detecting means for detecting whether or not word line switching has occurred; and when reading data held in a memory cell continuously, the word line switching detecting means switches the word line. 2. The read-only memory according to claim 1, wherein the control means does not discharge the sub-bit line when no detection is performed.