JPH1195979A - Integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the mounting density and to enable a high-speed operation, by providing an arithmetic part for performing the same operation for plural lines, a constitution information holding part for holding constitution information and a control part for controlling processing at the arithmetic part, and constituting a circuit again based on the constitution information determining the constitution of this circuit. SOLUTION: This device is provided with a control part 7 for outputting the constitution information determining the constitution of a reconstitutable circuit, constitution information holding part 1 for holding this constitution information, and arithmetic part 6 for performing the same operation plural times while constituting the circuit again based on this constitution information. The constitution information of each arithmetic part 6 outputted from the control part 7 is held in the constitution information holding part 1. This constitution information is outputted through wiring 3a and 3b to each arithmetic part 6. Each arithmetic part 6 outputs arbitrary wiring 3 through wiring 5 to the plural arithmetic parts 6 so as to perform the same operation plural times. Thus, since this device is constituted by collecting units for performing processing, the area of the constitution information holding part 1 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly, to an integrated circuit device capable of reconfiguring logic according to an application.

[0002]

2. Description of the Related Art PLDs (Programmable Logic Devices) and FPGs in which a user can freely configure or change the logic.
FPD such as A (Field Programmable Gate Array)
(Field Programmable Device) has attracted attention as a device that is extremely effective in shortening the development period because it can respond to changes in functions and circuits during the development of electronic devices.

[0003] In recent years, FPDs have been rapidly advanced in high integration, high speed, low power consumption, and low price. However, since the FPDs include extra circuits and switches, the mounting of the circuits is smaller than that of ordinary integrated circuits. Low density and low operating speed. Therefore, although effective in shortening the development period described above, it has not been applied to fields where performance is important such as operation speed and cost.

Therefore, if an FPD having a high mounting density and a high operation speed can be realized, it can be applied not only to shortening the development period but also to a field where performance is important, and the logic can be reconfigured according to the application. Integrated circuit devices and even
A more advanced integrated circuit device having a plurality of different functions can be realized by dynamically changing the configuration of a part of the logic of the operating integrated circuit device.

FIG. 4 shows a Xilinx XC6200 series FPGA cell as an example of an FPGA. This FPGA has a function unit (Function Uni
t) 11 and a plurality of multiplexers (MUX) 13, 1
5, 17, 19, 21, 22, 23, and 25.
The function unit 11 receives control signals and data from these multiplexers and the like, configures the unit according to the control signals, and outputs a result for the input data.

FIG. 5 is a diagram showing a function unit in a cell. This function unit 11
It is composed of multiplexers 27, 29, 31, 33, 37 and a register 35, and receives input signals X1, X2, X3 and performs a predetermined output F.

The XC6200 series is a dynamically reconfigurable FPGA that reconfigures some cells without affecting the cells that are not reconfigured to operate and achieves different functions. It is.

The cell is composed of thirteen multiplexers, one register, and a plurality of inverters for performing a NOT logic operation on the input / output of the multiplexer, and each multiplexer selects which signal is to be passed. Thus, any two-input logic gate can be realized as shown in FIG.

To configure a circuit function in a cell, FIG.
Although not shown in FIG. 5, each multiplexer is provided with a memory called a configuration memory for holding configuration information. In the XC6200, an SRAM is used as a configuration memory.

FIG. 7A is a diagram showing a configuration example of an arithmetic circuit. Here, the configuration memory M1
And two SRAMs M2 and M2 determine which of the four inputs of the four-input one-output (4: 1) multiplexer 41a is passed or output, and the circuit configuration is determined. These two SRs
Since four types of signals can be output by the AM, the multiplexer 41a can select one of the four inputs. The 8: 1 multiplexer requires a 3-bit SRAM, and the 16: 1 and 32: 1 multiplexers require a 4-bit and 5-bit SRAM, respectively. Also, in the cell shown in FIG. 4, the MUX 13 has 3 inputs because it has 8 inputs, the MUX 15 has 2 bits because it has 4 inputs, the MUX 17 has 3 bits because it has 8 inputs, and the MUX 19 has 2 bits because it has 4 inputs. MU
In X21, one bit is required because of two inputs, in MUX22, two bits are required because of four inputs, in MUX23, two bits are required because of four inputs, and in MUX25, three bits are required because of eight inputs. Further, each multiplexer in FIG. Since a total of 6 bits are required to select the input of
In total, one cell requires 24 bits of SRAM.

By inputting configuration information to these SRAMs from outside the cell and specifying the function of the cell, the two-input logic gate shown in FIG. 6 can be realized. And FPGA
During operation, the configuration information of some cells can be rewritten, and the circuit configuration formed by the FPGA can be dynamically changed and the function can be reconfigured.

In addition, not only cells but also wiring between cells can be reconfigured in the same manner. FIG. 7B shows an example of this, in which wiring from four directions to which signal is passed is determined by the six SRAMs M1 to M6 to configure signal wiring. For example, SRAM (M
When valid configuration information is held in 1), a signal is transmitted from top to left or vice versa.

As described above, by using the FPGA, the user can freely set an arbitrary circuit, and can dynamically reconfigure the circuit. From this, it is possible to easily cope with trial and error and function change in the development process of the electronic device, which is effective for shortening the development period. It is also suitable for application to electronic devices that make only a small amount.

Next, regarding the cryptographic processing integrated circuit, the FPD
The case where is applied will be described. Various cryptographic processing algorithms have been disclosed. One of them is NTT.
FEAL-8 disclosed by the company (Japanese Patent Publication No. 6-90)
597).

FIG. 9 shows a key processing unit for generating an extended key by inputting the FEAL-8 encryption key. FIG. 8 shows a function fK in the key processing unit shown in FIG. FIG. 11 shows an encryption processing unit for converting a plaintext into a ciphertext and an encrypted text into a plaintext using an expanded key. FIG. 10 shows a function f of the encryption processing unit shown in FIG. The key processing and the encryption processing are each repeated eight times by the function fK and the function f to increase the randomness of the data,
Increases the strength as a cipher. The number of repetitions is called the number of steps.

In the FEAL-8, both the key processing unit and the encryption processing unit are input with 64-bit data divided into left and right 32-bit data. The 32-bit data is a function fK and f is α1, α2, α3, α4 or β
The data is divided and input into four groups of eight bits, namely, 1, β2, β3, and β4. That is, arithmetic processing is performed in units of 8 bits.

In the integrated circuit, a plurality of bits n
In many cases, processing and calculation are performed in units of (n> 1).
In particular, in many cases, processing / operation is performed in units of even-numbered bits, in other words, 2n bits.

In the functions fK and f, a circle is indicated by a + sign (EXO
R) and the function Si (i = 1, 0) operator,
R is an exclusive OR corresponding to 8 bits, and the function Si (i = 1, 0) adds two 8-bit inputs,
After adding i, an operation of rotating left by 2 bits is performed.

The detailed operation of FEAL-8 will be omitted. Cryptography is always the key to cracking attacks. Therefore, by making the cryptographic integrated circuit reconfigurable by the PLD, a part of the operator or the connection of the data line between the operators is changed from time to time or periodically or every time a cipher text is sent, so that the The processing of the sentence changes, and an encryption processing integrated circuit that is extremely difficult to break can be realized. This is an effective field of application for reconfigurable integrated circuits.

Here, it is needless to say that the FPGA shown in FIGS. 4 and 5 can be used. In this case, for example, when an exclusive OR of 8 bits is formed, a minimum of 8 cells including a 24-bit configuration SRAM is required. This is not preferable in terms of mounting density as described above.

[0021]

SUMMARY OF THE INVENTION As described above, the FPGA
However, there is a disadvantage that the circuit density is low and the operation speed is low. First, looking at the packaging density, for example, in a normal integrated circuit (called hard-wired logic) composed of fixed elements and wiring, taking a two-input NAND gate that can be configured with four transistors as an example, FPG
A consumes many multiplexers and inverters as shown in FIGS. Further, a configuration memory equal to or more than a multiplexer is required. In FPGA, 1/1 of hard-wired logic
It is said that only a mounting density of 10 or less can be achieved.

Next, as for the operation speed, taking a 2-input NAND gate as an example, in the case of a hard-wired logic, a signal only passes through a single-stage gate.
In the FPGA, as shown in FIGS. 4 and 5, the signal passes through at least four multiplexers and some inverters. Therefore, in the FPGA, the signal propagation delay time is delayed. It is said that the operation speed is about 10 times lower than that of hard-wired logic.

For these reasons, it is difficult to apply the FPGA to a field where cost performance is important.

On the other hand, the number of elements that can be mounted on a silicon chip has increased dramatically due to advances in integrated circuit manufacturing technology.
Attempts have been made to realize the versatility of an integrated circuit, which has been conventionally achieved by microprogram control, with reconfigurable hardware by utilizing the increased mountable elements. Here, if a reconfigurable integrated circuit that operates at high speed is realized, in addition to flexibility and versatility, it will have the high processing power that was the only unique integrated circuit using hard-wired logic. A new integrated circuit can be realized.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an integrated circuit device capable of dynamically reconfiguring logic, having a high packaging density and operating at high speed. Is to do.

[0026]

According to a first aspect of the present invention, there is provided an arithmetic unit for performing reconfiguration based on configuration information for determining a configuration of a circuit and performing a plurality of identical operations; It is characterized by comprising a configuration information holding unit for holding information, and a control unit for controlling processing of the arithmetic unit.

In the configuration of the present invention, the arithmetic unit performs reconfiguration based on the configuration information and performs a plurality of identical operations. Here, the operation includes not only the operation performed by a single gate having a fine granularity such as exclusive OR, but also a medium-scale operation such as an adder and a multiplier, and a large-scale operation such as an ALU.

As described above, when a plurality of identical operations are performed, they are configured collectively for each processing unit, that is, reconfigured based on the same configuration information, so that the mounting density can be improved. It is. The processing unit may be a function unit or a processing unit including a plurality of function units. Here, the reconfigurable integrated circuit includes both a case where all of them are reconfigurable and a case where a part thereof is reconfigurable. Further, the configuration information holding unit may be any unit that can store information and can read and write.

According to a second aspect of the present invention, the arithmetic unit according to the first aspect includes a circuit for performing a fixed operation by hard wiring.

As described above, by performing the fixed arithmetic operation by using a hard wire, the processing density can be further improved, and the processing speed can be further improved. That is, since a part or the whole of the arithmetic unit is hardwired, an extra circuit and a switch required when a reconfigurable circuit is not required, the mounting density can be further improved. In addition, since no extra circuits or switches are required, the processing speed can be improved.

According to a third aspect of the present invention, the arithmetic unit according to the first aspect performs a first partial circuit for performing a predetermined operation by reconstructing from a plurality of bits of the configuration information held in the configuration information holding circuit. And a second partial circuit for performing a fixed operation by hard wiring, wherein a mutual connection relationship between the second partial circuits can be reconfigured by the first partial circuit. And

In the configuration of the present invention, a second partial circuit for performing a fixed operation by hard wiring is prepared.
The mutual connection relationship can be reconfigured. By doing so, the processing speed can be further improved, in addition to the further improvement of the mounting density, for the reasons described above.

The invention according to a fourth aspect is characterized in that the control unit according to the first to third aspects is a reconfigurable circuit.

In the configuration of the present invention, the control unit for controlling the arithmetic unit is a reconfigurable circuit. By making it reconfigurable in this way, it is possible to change the procedure of the processing performed by the arithmetic unit.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the integrated circuit device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an integrated circuit device according to the first embodiment. The integrated circuit device includes a control unit 7 that outputs configuration information that determines a configuration of a reconfigurable circuit, a configuration information holding unit 1 that holds the configuration information, and performs reconfiguration based on the configuration information. And an operation unit 6 that performs a plurality of identical operations. The configuration information of each operation unit output from the control unit 7 is stored in the configuration information storage unit 1. This configuration information is output to each operation unit 6 via the wirings 3a and 3b. Arbitrary wiring of the wiring 3 is output to the plurality of processing units via the wiring 5 so that each processing unit 6 performs a plurality of identical calculations. As described above, since the units for performing the processing are configured collectively, the area of the configuration information holding unit 1 can be reduced. Therefore, the mounting area can be reduced.

Here, the operation may be an operation performed by a single gate having a fine granularity such as an exclusive OR, a medium-scale operation such as an adder or a multiplier, or a large-scale operation such as an ALU. . Then, instead of individually combining functional circuits one by one to configure or reconfigure an integrated circuit having a desired function, a unit for performing processing is configured or reconfigured collectively.

The control unit 7 uses an FPGA which is a reconfigurable circuit. By using the FPGA as described above, the procedure of the processing performed by the arithmetic unit can be changed.

Here, the case where this embodiment is applied to the circuits shown in FIGS. 9 and 11 will be described. FIG.
Here, the arithmetic processing unit represented by the function fK and the function f is configured to be the arithmetic unit 6. This includes the registers for storing the intermediate results of the processing and the operators such as the exclusive OR and the function Si shown in FIG. 8 and FIG. 10, and the data lines connecting them.

Also, the processing of the eight stages of the circuits shown in FIGS. 9 and 11 may be all provided as circuits, and since the processing of each stage is similar, a smaller number of stages, for example, one stage, two stages,
An eight-stage process may be performed by incorporating only four-stage and four-stage circuits and repeatedly using them. When reconfigurable by an FPGA or the like, the scale becomes large. Therefore, it is better to mount only a smaller number of stages and repeatedly use them.

Here, the control unit 7 shown in FIG. 1 shows a circuit for controlling the processing of the arithmetic unit 6, for example, for synchronizing the processing of each operator, controlling the number of repetitions of the number of steps processing, and inputting it to the function f. Control to select an expanded key to be executed. In addition, since the control unit 7 is not always a process that uses 8-bit data as a unit as in the arithmetic unit 6, a configuration SRAM is provided for each circuit.

The configuration information holding unit 1 shown in FIG.
Although the AM is used, the configuration information held in one of the SRAMs is sent in common to an 8-bit arithmetic unit as shown in FIG. 1 so as to configure an 8-bit analogous circuit. is there.

In this embodiment, attention is paid to the fact that the cryptographic processing integrated circuit of FIGS. 9 and 11 performs processing in units of 8 bits, that is, the corresponding portions of each bit have the same circuit configuration. Paying attention to this fact, the configuration information of the circuit of the arithmetic unit is provided collectively for each processing unit instead of being provided for each bit. As a result, the number of configuration SRAMs can be reduced and the packaging density can be improved.

In the FEAL-8, the arithmetic processing is performed in units of 8 bits. Therefore, as shown in FIG.
M provides configuration information. As a result, the configuration SRAM is reduced to 1/8 of that of the FPGA, and the overall mounting density is greatly improved. Now, assuming that the area of an element that performs an operation such as a multiplexer and an inverter in an FPGA and the area of an SRAM for configuration are 1: 1, according to the present invention,
The area occupied by the operation unit in FIG. 1 is reduced to 56% as compared with a case where the configuration information of the circuit of the operation unit is given for each bit.

As described above, in the present embodiment, the packaging density can be greatly improved by configuring the processing units collectively.

FIG. 2 is a diagram showing an integrated circuit device according to the second embodiment. The body integrated circuit device outputs a configuration information for determining a configuration of a reconfigurable circuit, a configuration information holding unit 1 for holding the configuration information, and performs reconfiguration based on the configuration information. , An arithmetic unit 9 for performing a plurality of identical operations, and the arithmetic unit 9 is configured to perform fixed arithmetic operations by hard-wiring. In FIG. 1, the exclusive OR of the operation unit, the function Si, the register for storing the intermediate result of the processing, and the like are also reconfigured one gate at a time using a PLD such as an FPGA. The implementation density of each operator is low and the processing speed is slow.

Therefore, in FIG. 2, the exclusive OR, the function S
Operators such as i and registers or functional circuits are created as hard-wired logic, and how these functional circuits are connected can be reconfigured. At this time, reconstruction is performed for each processing unit similar to that in FIG. According to the integrated circuit device of the present embodiment, not only the mounting density but also the processing speed can be improved.

FIG. 3 is a diagram showing an integrated circuit device according to the third embodiment. The integrated circuit device includes a control unit 7 that outputs configuration information that determines a configuration of a reconfigurable circuit, a configuration information holding unit 1 that holds the configuration information, and performs reconfiguration based on the configuration information. Arithmetic unit 9 that performs a plurality of identical operations
The arithmetic unit 9 is configured to perform fixed arithmetic by hard-wired. Also in this embodiment,
Operators or functional circuits such as an exclusive OR, a function Si, and a register are created as hard-wired logic, and how these functional circuits are connected can be reconfigured. At this time, reconstruction is performed for each processing unit similar to that in FIG. According to the integrated circuit device of the present embodiment, not only the mounting density but also the processing speed can be improved.

This integrated circuit device is used, for example, in FIGS.
When applied to one circuit, one piece of configuration information is sent in common to an 8-bit arithmetic circuit so that a similar 8-bit arithmetic circuit is configured. In this case, the mounting density of the hard wire logic is improved by one digit or more and the processing time is reduced to about 1/10 as compared with the PLD such as the FPGA, so that the arithmetic unit of FIG. 2 has a larger area than that of FIG. Is 1/10
The processing speed is improved to about 10 times.

In the embodiment of FIG. 1, it is difficult to incorporate the entire number of processing steps in terms of area, and the encryption processing is performed by incorporating a small number of steps and repeatedly using them. In the embodiment of FIG. 3, the area is 1/10 or less. As a result, it becomes possible to easily implement all the processing stages. By doing so, each stage is used only once for one ciphertext process, so that ciphertexts can be input from one to the next and subjected to cryptographic processing. By mounting all eight stages, the processing capacity is improved eight times compared to the case where only one stage is mounted.

As described above, the circuit is hard-wired in functional circuit units, and the hard-wired functional circuits are collectively configured and reconfigured in one set of configuration memories in units of bits for arithmetic processing, thereby implementing the circuit. Both the density and the processing capacity can be greatly improved.

Here, a functional circuit is a single gate having a fine granularity such as an exclusive OR, a medium-scale arithmetic circuit such as a function Si, an adder or a multiplier, or a large-scale arithmetic circuit such as an ALU. It may be a circuit. Then, the functional circuits are individually combined one by one to form an integrated circuit having a desired function,
Alternatively, instead of reconfiguring, processing units are collectively configured or reconfigured.

The configuration memory for holding the configuration information may be an SRAM as described above, a so-called FRAM using a ferroelectric material, or any element that can read / write / store information. . However, if a non-volatile memory such as FRAM is used,
Even when the power is turned off, the configuration information is retained, so that it can be used in a field where such a case is assumed.

Although the FPGA is used as the reconfigurable circuit in the present embodiment, the present invention is not limited to this.
A reconfigurable PLD such as A can also be used.

Here, the integrated circuit device for cryptographic processing has been described as an example. However, any integrated circuit device that performs arithmetic and processing in units of a plurality of bits and in which a part of the circuit can be configured or reconfigured into a desired circuit can be used. If so, the present invention is effective.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0057]

As described above, according to the integrated circuit device of the present invention, an integrated circuit capable of dynamically reconfiguring logic is operated at a high mounting density and at a high speed. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an integrated circuit device according to a first embodiment.

FIG. 2 is a diagram illustrating an integrated circuit device according to a second embodiment.

FIG. 3 is a diagram illustrating an integrated circuit device according to a third embodiment.

Fig. 4 Xilinx XC6200 series FPG
FIG. 3 is a conceptual diagram showing a cell A.

Figure 5: Xilinx XC6200 series FPG
FIG. 3 is a diagram showing a function unit of a cell A.

Figure 6: Xilinx XC6200 Series FPG
FIG. 3 is a diagram for explaining a two-input logic gate that can be realized by the cell A.

FIG. 7 is a diagram for explaining a configuration SRAM of Xilinx XC6200,
(A) is an example of configuring an arithmetic circuit, and (b) is an example of configuring wiring.

FIG. 8 shows a function fK in the key processing flow.

FIG. 9 is a flowchart of a key process for generating an extended key by inputting an encryption key using the FEAL-8 algorithm.

FIG. 10 shows a function f in the cryptographic processing unit.

FIG. 11 illustrates an encryption processing unit that converts a plaintext into an encryption unit or an encrypted text into a plaintext using an expanded key.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Configuration information holding information (SRAM) 3,5 Wiring 6,41 FPGA cell 7 Control part FPGA 9 Hard-wired cell 11 Function unit 13,15,17,19,21,22,23,25,2
7, 29, 31, 33, 37, 39, 43 Multiplexer 35 Flip-flop

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yuji Sekine 1 Toshiba R & D Center, Komukai Toshiba-cho 1

Claims (4)

[Claims] 1. An arithmetic unit for performing reconfiguration based on configuration information for determining a circuit configuration and performing a plurality of identical operations, a configuration information holding unit for holding the configuration information, and controlling processing of the arithmetic unit. An integrated circuit device comprising: a control unit. 2. The integrated circuit device according to claim 1, wherein the operation unit includes a circuit that performs a fixed operation by hard wiring. 3. A first partial circuit for performing a predetermined operation by reconstructing a plurality of bits of the configuration information held in the configuration information holding circuit and performing a predetermined operation, and a fixed operation by hard wiring. 2. The integrated circuit according to claim 1, further comprising: a second partial circuit that performs the following: and wherein the mutual connection relationship of the second partial circuits can be reconfigured by the first partial circuit. apparatus. 4. The integrated circuit device according to claim 1, wherein the control unit is a reconfigurable circuit.