JPH1188790A - Pll feedforward circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a demodulation output free from horizontal jitter noise by generating a carrier of a specified frequency synchronizing with an IF signal from a VCO frequency generated by a 1st PLL circuit on the inside of a tuner, and allowing an IF circuit to demodulate the IF signal with a carrier of a specified frequency. SOLUTION: A frequency of a VCOA 4 is frequency-divided by a program counter Q13 to obtain a carrier of 58.75 MHz phase-locked to an IF signal, and a tuner section 1 outputs a 58.75 MHz carrier obtained by band-pass-filtering the 58.75 MHz component at a filter 14 to an IF section 2. The IF section 2 uses the 58.75 MHz carrier of the reference oscillation component as the 58.75 MHz carrier from the tuner section 1 and a demodulation output without horizontal jitter is obtained by using a synchronization detection circuit 16 to demodulate the 58.75 MHz carrier phase-locked with the IF signal and the IF signal itself. Thus, a clear image free from horizontal jitter noise is viewed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL feed-forward circuit, and more particularly, to a tuner having a PLL circuit system of a video signal receiving apparatus and a receiving apparatus for an IF circuit.

[0002]

2. Description of the Related Art A demodulation circuit using a conventional PLL (phase locked loop) circuit will be described with reference to FIG. In the PLL circuit of the tuner 1, the oscillation frequency of the VCO (voltage controlled oscillator) 4 is divided by the prescaler 6, the program counter 7, and the swallow counter 8 and input to the phase comparator 9.
This signal and the reference oscillator 12 are transferred to the reference counter 11
Is compared with the phase of the divided signal, and the output is compared with the error L
The VCO 4 is corrected by smoothing with the PF 5 to generate a VCO frequency, and the mixer 3 multiplies the VCO frequency by the RF signal to convert the frequency to an IF (intermediate frequency) signal.
The F signal is input to the next-stage IF circuit 2. In the IF circuit 2, the reference oscillation frequency of the VCO 18 is compared with the IF signal by the phase comparator 17, the error is smoothed by the LPF 19, the VCO frequency is created by the PLL circuit for correcting the VCO 18, and demodulated by the synchronous detection 16. I do. As described above, the PLL circuit of the tuner unit 1 and the PLL circuit of the IF unit 2 have independent configurations.

[0003]

As described above, in the demodulation circuit using the conventional PLL circuit, the PLL circuits of the tuner unit 1 and the IF unit 2 operate independently. Since the phase of the VCO frequency is not completely synchronized, the demodulated output at the synchronous detection 16 is H
(Horizontal) jitter noise is included. P of IF unit 2
The LL circuit should be able to demodulate by the synchronous detection 16 by the VCO frequency synchronized with the IF signal. However, due to the frequency characteristics of LPF,
When the frequency of the error signal is equal to or lower than the cutoff frequency, the signal detected by the comparator 17 can be followed in the process of smoothing the error signal, and a demodulated output free from H jitter noise can be obtained. If the frequency of the error signal is equal to or higher than the cutoff frequency, the error signal cannot be followed, so that the VCO frequency cannot be synchronized with the input IF signal, and H jitter noise is included. In the case of the error signal, there is a disadvantage that the original characteristics of the PLL circuit cannot be obtained. This will be described with reference to FIG.

In order to perform frequency conversion by the mixer 3,
The RF signal (A) and the VCO frequency (B) are input to a mixer, and the obtained mixer 3 output (C) is used as an IF. FIG.
The graphs of (A) and (B) show the RF signal and V, respectively.
The time change of the frequency of CO4 is shown, and the graph of (C) shows the time change of the output frequency of the mixer 3. From these graphs, it can be seen that the RF signal (A) is a pure carrier having no frequency change with respect to time change.
It is clear that the O frequency (B) is a carrier including a phase shift whose frequency changes with time. The output of the mixer 3 is also a carrier including a phase shift similarly to the VCO frequency, and is an IF signal output, as is apparent from the graph of FIG. Where V
The phase shift of the CO frequency is a peculiar symptom of the PLL that always occurs due to the PLL circuit.

The IF signal (C) including this phase shift and VC
The pure carrier which is the output (D) of O18 is compared by the phase comparator 17, and the error output is converted into DC by the LPF 19,
The VCO 18 is corrected (FIG. 3). In this case, if the phase shift frequency f of the IF signal (C) is equal to or lower than the cutoff frequency of the LPF 19, the signal can be followed. Therefore, the VCO frequency becomes (F), and the phase-synchronized IF signal (C) and the VCO frequency ( The result of synchronous detection of F) is as shown in the graph of (G) in the figure, and a demodulated output without H jitter noise can be obtained. However, if the phase shift frequency of the IF signal is equal to or higher than the cutoff frequency, the signal cannot be followed, and the VCO frequency is as shown in the graph (D). If the phases are not synchronized in this way, the result of synchronous detection of the IF signal (C) and the VCO frequency (D) is as shown in the graph (E), and the X axis is TV LINE,
If the Y-axis is H jitter, there is a problem that the horizontal phase is shifted on the TV line and appears on the screen as H jitter.

[0006]

SUMMARY OF THE INVENTION The present invention relates to the conventional PL.
The present invention has been made to solve the problem in the L feedforward circuit, and the invention of claim 1 is a PLL feedforward circuit for demodulating an IF signal from a tuner by an IF circuit, wherein the tuner is a first feeder. Means for generating a carrier of a specified frequency synchronized with the IF signal from a PLL circuit and a VCO frequency generated by the first PLL circuit, and the IF circuit converts the IF signal with the carrier of the specified frequency. This is a PLL feedforward circuit having a synchronous detector for demodulation.

According to a second aspect of the present invention, there is provided a PLL according to the first aspect.
A feedforward circuit, wherein the tuner PL
The specified frequency generated from the VCO frequency generated by the L circuit is 58.75 MHz, and the means for generating the 58.75 MHz carrier includes a program counter for dividing the VCO frequency and 58.75 MHz of the frequency divider output. The PLL feedforward circuit having a filter for extracting a component.

According to a third aspect of the present invention, in the PLL feedforward circuit according to the first or second aspect,
The IF circuit has a second PLL circuit, and sets a reference oscillation frequency of the synchronous detector for demodulating the IF signal to IF
The PLL feedforward circuit further comprising switching means for switching to a VCO frequency generated by a second PLL of the circuit or to the 58.75 MHz carrier generated by the tuner.

According to a fourth aspect of the present invention, there is provided the PLL according to the third aspect.
In the feedforward circuit, the switching means may be a PL.
The PLL controlled by an AND circuit for generating a logical product of an L lock detection signal and a control signal from a microcomputer.
It is a feed forward circuit.

[0010]

1 and 2 show an embodiment of the present invention.
Will be described with reference to FIG. The local oscillation frequency of the VCO 4 in the tuner is pre-divided by P / P + 1 by the prescaler 6, and N and S are respectively divided by the program counter 7 and the swallow counter 8.
Divided. The comparison frequency fP obtained by this,
The phase comparator 9 compares the frequency 4 MHz of the reference oscillator 12 with fR obtained by dividing the frequency by the reference counter 11, and D / A converts the obtained error signal by the charge pump 10. A PLL loop for DC smoothing by the LPF 5 and correcting the VCO 4 is formed, the oscillation frequency of the VCO 4 is frequency-converted by the RF signal and the mixer 3, and an intermediate frequency (IF signal) of 58.75 MHz is output from the tuner.

The above tuner operation has the same configuration as the conventional PLL selection system. In this method, the oscillation frequency of the VCO 4 is generally a signal whose C / N is degraded due to noise noise, and is a signal that has been subjected to phase modulation in which the frequency changes over time (FIG. 2 ( B)). Therefore, the VCO 4 signal (FIG. 2B) and the RF signal (FIG.
(A)) is converted to an IF signal (FIG. 2 (C)).
It is output as a signal having the same phase noise as that of CO4.

Therefore, according to the present invention, the frequency of the VCO 4 is divided by the program counter 13, a carrier of 58.75 MHz is obtained, and a 58.75 MHz carrier obtained by band-passing the 58.75 MHz component by the filter 14 is output from the tuner. The data is input to the IF unit 2. This signal is a signal that is phase-synchronized with the VCO, and is also a signal that is phase-synchronized with the IF signal (FIG. 2D).

Next, the IF demodulation operation will be described. IF
The basic operation of demodulation is the IF signal and the reference oscillation of 58.75M
To obtain a demodulated output by synchronously detecting a frequency carrier. In the present invention, the reference oscillation is 58.75 MHz.
The z-carrier is 58.75M for obtaining the demodulated output.
2 (E), and the IF signal is phase-synchronized with the IF signal and the IF signal is demodulated by the synchronous detection 16 to obtain the signal shown in FIG. As shown in the figure, it is possible to obtain a demodulated output having no displacement (no H jitter). In other words, a clear screen without horizontal jitter noise can be viewed.

Further, the present invention has a switching control unit 20 for switching the reference oscillation in the synchronous detection 16 to a conventional PLL IF demodulation system. This switching control unit includes a PLL
When the feedforward circuit is used as a conventional PLL IF demodulation system, that is, the oscillation frequency of the VCO 18 and the IF signal are compared by the phase comparator 17, and the error signal obtained from the comparison is smoothed by the LPF 19, and
VCO made by PLL loop to correct CO18
It is possible to switch between demodulation using a frequency and demodulation using a 58.75 MHz carrier.

The control signal of the switching control unit 20 is based on an AND of the PLL lock detection signal in the tuner and the microcomputer IC signal.
The output is controlled by the D output, the lock is performed when the PLL lock detection signal is “1”, and the PLL is controlled when the PLL lock detection signal is “0”.
Input to the AND circuit as L unlock. The control signal from the microcomputer is “1” when demodulation according to the present invention is performed,
When performing normal demodulation, "0" is input. The AND circuit receives the PLL lock detection signal and the control signal from the microcomputer and outputs "1" or "0". When the output is "1", the switching means switches the detection means to 58.75 so as to use the detection system of the present invention.
The frequency is switched to the MHz carrier, and if "0", it is switched to the reference signal of the normal detection system. That is, only when the PLL lock detection signal and the microcomputer IC signal are “1”,
The switching control unit 20 is switched so that the frequency of the present invention is input to the synchronous detection 16 as a reference frequency, and when the AND output becomes “0”, the switching control unit 20 is set so that the conventional frequency becomes the reference frequency. Switch to.

This IF demodulation reference frequency switching means uses, for example, the conventional reference frequency at the time of channel switching and the conventional reference frequency at the time of channel switching. Or the demodulation on the audio side uses the conventional PL
Since it is better to perform 4.5 MHz demodulation with a VCO formed by an L loop, the reference frequency can be forcibly switched, for example, by maintaining the state of a conventional PLL circuit. You can choose.

[0017]

The effect corresponding to the first and second aspects of the present invention: I
The reference frequency required for F demodulation is synchronized with the specified frequency (58.7) obtained by dividing the VCO in the tuner, which is phase-synchronized with the IF signal.
By demodulating as a 5 MHz) carrier, an effect of being able to view a clear screen without H jitter noise can be obtained. Effects corresponding to Claims 3 and 4: In addition to the effects corresponding to Claims 1 and 2, the reference frequency is set to 58.75 MH.
Since a means for switching from the z carrier to the reference frequency of the conventional PLL demodulation system is provided, it is possible to select the reference frequency, and to shorten the switching time at the time of channel switching. It is also possible to obtain the effect that the user can freely select the reference frequency at the time of demodulation, such as switching the frequency to the carrier after the selection is completed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL feedforward circuit of the present invention.

FIG. 2 is a diagram showing characteristics of each signal and H jitter in an embodiment of a PLL feedforward circuit of the present invention, wherein A is an RF signal, B is a VCO 4 signal, C is an output of the mixer 3, FIG. 6D is a diagram showing a time change of the output of the program counter 13, and FIG. 9E is a diagram showing a change of the jitter component of the demodulation detection output with respect to the TV line.

FIG. 3 is a block diagram showing a conventional PLL feedforward circuit.

FIG. 4 is a diagram showing characteristics of each signal and H jitter in a conventional PLL feedforward circuit, where A is R;
The F signal, B is the signal of the VCO 4, C is the output of the mixer 3, D and F are the time changes of the signal of the VCO 18, and E and G are the time changes of the H jitter component of the demodulation detection output 15. FIG.

[Explanation of symbols]

1. Tuner section, 2. IF section, 3. Mixer, 4. VC
OA, 5 ... LPFA, 6 ... Prescaler, 7 ... Program counter N, 8 ... Swallow counter S, 9 ... One phase comparator, 10 ... Charge pump, 11 ... Reference counter, 12 ... Reference oscillator, 13 ... Program counter Q ,
14: filter, 15: AND circuit, 16: synchronous detection, 17: phase comparator, 18: VCOB, 19: LPF
B, 20: switching control unit.

Claims (4)

[Claims] 1. A PLL feed-forward circuit for demodulating an IF signal from a tuner by an IF circuit, wherein the tuner generates a first PLL circuit and the IF signal from a VCO frequency generated by the first PLL circuit. Means for generating a carrier of a specified frequency to be synchronized, and
A PLL feedforward circuit having a synchronous detector in which an F circuit demodulates the IF signal with the carrier having the specified frequency. 2. The PLL feedforward circuit according to claim 1, wherein a specified frequency generated from a VCO frequency generated by the PLL circuit in the tuner is 58.75 MHz.
z, wherein the means for generating the 58.75 MHz carrier includes a program counter for dividing the VCO frequency and a filter for extracting a 58.75 MHz component of the divider output. PLL feedforward circuit. 3. The PL according to claim 1, wherein
In the L feed-forward circuit, the IF circuit has a second PLL circuit, and sets a reference oscillation frequency of the synchronous detector for demodulating the IF signal to a second PLL circuit of the IF circuit.
Switching means for switching to the VCO frequency generated by L or the 58.75 MHz carrier generated by the tuner. 4. The PLL feed-forward circuit according to claim 3, wherein said switching means is switched by an AND circuit that generates a logical product of a PLL lock detection signal and a control signal from a microcomputer.
Feedforward circuit.