JPH1188354A - Data buffer switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the access waiting time for a memory and to shorten the data transfer delay time of a device at the time of accessing to a memory from each port by individually reading out each packet that is received and dispersively written in each memory and outputting it in each port. SOLUTION: One cycle of each port is allocated to a time slot for the number of ports. A memory access control part 4 returns an access response signal (a) to request signals a from ports 21 to 24, simultaneously, outputs a select signal (b) to selectors 31 to 34 and transmits a memory control signal (c) to memories 11 to 14. Thereafter, the memory access control part 4 successively generates and outputs the select signal (b) to the selectors 31 to 34 and a control signal (c) to the memories 11 to 14. An address signal to be outputted to a memory is generated by a buffer management function part in the memory access control part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network connection device for interconnecting networks, and more particularly to a data buffer switch for exchanging packets (continuous data) input to the network connection device.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram showing a configuration of a main part of a conventional network connection device for interconnecting networks, and shows a configuration of a data buffer switch for performing a process of exchanging packets input from the network. Things. The data buffer switch includes memories 11 to 14 for storing packets, ports 21 to 24 for accessing the memories 11 to 14, and a selector 3 for switching connection between the ports 21 to 24 and the memories 11 to 14.
1 to 34, and a memory access control unit 4 for controlling connection between the ports 21 to 24 and the memories 11 to 14 are provided. In the figure, the bold line indicates packet data, a is a port control signal for controlling a port, b is a select signal for switching control of a selector, and c is a memory control signal for controlling a memory. In FIG. 8 and each of the drawings described later, memories # 1 to # 4 correspond to memories 11 to 14, ports # 1 to # 4 correspond to ports 21 to 24, and selectors # 1 to # 4.
# 4 corresponds to the selectors 31 to 34, respectively.

Here, when a received packet from a network (not shown) is input from, for example, the port 21, the received packet is written into the memory 11 and temporarily stored. For example, an input packet via the port 22 is written to the memory 12. Further, an input packet via the port 23 is written into the memory 13, and an input packet via the port 24 is written into the memory 14.

When transmitting the received packets stored in the memory, the memory access connection unit 4 controls the switching of the selectors 31 to 34 and, for example,
Is read out from an arbitrary port 22. FIG. 9 is a diagram showing an access state of the memory of the conventional device. Packet data (A1 to A4, B1 to B4) from port # 1 (that is, port 21) is stored in the corresponding memory # 1 (that is, memory 11). Is written to. Also, the packets C1 to C4, D1 to D4, and E1 to
E4 is read from ports 22, 23 and 24, respectively. As described above, when reading data from the memory, the data is read from an arbitrary port.

[0005]

By the way, the port 21
When reading and transmitting the packet data written in the corresponding memory 11 from the corresponding port, there is a problem that contention for access to the memory 11 occurs between a plurality of arbitrary read ports. Therefore, it is not possible to read from the next port until reading from one port is completed, and there is a problem that it takes a long time to read.

That is, the packet data written from the port 21 to the corresponding memory 11 is transferred to the ports 22, 23, 24.
10, as shown in FIG. 10, first, reading is performed from the port 22 (FIG. 10B), and when this is completed, reading is performed from the port 23 (FIG. 10).
(C)) After the reading of the port 23 is completed, reading is performed from the port 24 (FIG. 10D). As described above, when read accesses from all ports are concentrated on one memory, the time required to multiply the packet length by the number of all ports (that is, the packet number) is required until reading of packet data from all ports is completed. There is a disadvantage that it takes (length × the number of all ports).

On the other hand, in recent years, with the speeding up of packets transferred between networks, the processing speed has also been required for this type of data buffer switch that exchanges and transfers packet data from the network. There is a demand for a reduction in the access waiting time for the memory of the port as described above. Therefore, an object of the present invention is to reduce the data transfer delay time of the device by shortening the access wait time for the memory when accessing the memory from each port.

[0008]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention provides a plurality of memories for storing packets, a plurality of ports for accessing the memories, and a connection between the ports and the memories. In a data buffer switch including a selector for switching and a control unit for controlling the selector and connecting between a port and a memory, writing into the control unit a packet received via the port in a distributed manner to each memory There are provided control means, and read control means for reading each packet distributed and written in each memory individually and outputting to each port. The control unit includes a memory management unit that manages a memory for each port, and the memory management unit allocates an arbitrary area of the memory to the port based on a preset setting. Further, the control unit is provided with a memory management unit for managing the memory in common for each port. Further, a bandwidth varying means for varying the bandwidth of all ports according to the number of memories to be accessed is provided.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the data buffer switch according to the present invention. In the figure, the switch switches memories 11 to 14 for storing packet data, ports 21 to 24 for accessing the memories 11 to 14, and switching of connections between the ports 21 to 24 and the memories 11 to 14. Selectors 31 to 3
4 and a memory access control unit 4 for controlling connections between the ports 21 to 24 and the memories 11 to 14. In the figure, the bold line indicates packet data, a is a port control signal for controlling a port, b is a select signal for switching control of a selector, and c is a memory control signal for controlling a memory. In FIG. 1 and each of the drawings described below, memories # 1 to # 4
1 to # 4 correspond to ports 21 to 24, and selectors # 1 to # 4 correspond to selectors 31 to 34, respectively.

Here, the plurality of memories 11 to 14 are arranged in parallel when viewed from the respective ports 21 to 24, and
By switching 1 to 34, data can be written to and read from all the memories 11 to 14 from the port side. When performing memory access control, as described later, time slots for the number of ports are provided in one cycle, and each time slot is assigned to each port.
, An access response signal is returned in response to an access request from the memory, and a select signal is sent to each of the selectors 31 to 34 so as to access the memories 11 to 14 in a fixed order. Send a control signal.

That is, when performing memory access control, 1
Time slots for the number of ports are allocated during the cycle. Here, when an access request signal to be described later is generated from the port to the memory, the memory access control unit 4 returns an access response signal to be described later in the time slot allocated to the memory, and outputs a select signal to the selector at the same time to output a select signal to the selector. And switches the connection with the memory and sends a memory control signal to the memory. As a result, the corresponding port can access the corresponding memory. Thereafter, the memory access control unit 4 sequentially generates and outputs a select signal to the selector and a control signal to the memory so that the memory can be accessed in a fixed order. For the address signal to be output to the memory, a buffer management function unit described later is provided in the memory access control unit 4 and generated by the buffer management function unit.

Thus, even when a read request is issued from a plurality of ports for transmission with respect to a packet input from one port, each packet is distributed and stored in a plurality of memories. The memory access waiting time can be reduced, and thus the data transfer delay time can be reduced.

FIG. 2 shows a second example of the data buffer switch.
It is a block diagram showing an embodiment. The data buffer switch of FIG. 2 transmits the port control signal a of the data buffer switch shown in FIG. 1 from the port to the access request signal a1 to the memory access control unit 4 and the memory access control unit 4 to the access response to the port. The memory access control unit 4 sends the address signal d to each memory.

FIG. 3 is a diagram showing an accumulation state of packet data in the data buffer switch shown in FIG. In this data buffer switch, packet data A1 to A4, B1 to B4 are transmitted from port 21 to A1, A2,
When data is input in the order of A3, A4, B1, B2, B3, and B4, the data A is stored in the memories 11, 12, 13, and 14, respectively.
1, A2, A3, and A4 are sequentially stored, and then stored in the memory 1
Data B1, B2, B3, B4 in 1, 12, 13, 14
Are sequentially accumulated.

In the memory 11, data C1, D1,
When data E1, data C2, D2, and E2 are stored in the memory 12, data C3, D3, and E3 are stored in the memory 13, and data C4, D4, and E4 are stored in the memory 14, respectively. Memory data is C1, C
2, C3, and C4, the data of each memory is read from the port 23 in the order of D1, D2, D3, and D4.
2, E3 and E4 are read out in this order.

FIG. 4 is a time chart showing a state of memory access based on the control of the memory access control unit 4 of the data buffer switch shown in FIG. The operation of the main part of the present invention will be described in detail with reference to the time chart of FIG. In this switch, as described above, each of the ports 21 to 2
4 each time slot ts1 to ts as shown in FIG.
4 are assigned, and this is one cycle. Now, when an access for writing the first packet from the port 21 is started in the time slot ts1 allocated to the port 21 in one cycle shown in FIG. 4, the packet from the port 21 is written to the memory 11. . In this case, the ports 22 to 24 are waiting for access.

Next, when an access for reading a packet from the port 22 is started in the time slot ts2,
The packet in the memory 11 is read out to the port 22. At this time, a packet is written to the memory 12 at the port 21, and the ports 23 and 24 are waiting for access.
Subsequently, when the access for reading the packet from the port 23 is started in the next time slot ts3, the packet in the memory 11 is read to the port 23. At this time, the port 21 writes a packet to the memory 13, and the port 22 reads a packet from the memory 12. The port 24 is waiting for access.

Next, when access for reading a packet from the port 24 is started in the time slot ts4,
The packet in the memory 11 is read out to the port 24. At this time, a packet is written to the memory 14 at the port 21, a packet is read from the memory 13 at the port 22, and a packet is read from the memory 12 at the port 23. Subsequently, when the access for writing the second packet from the port 21 is started in the next time slot ts5, the second packet from the port 21 is written to the memory 11. At this time, a packet is read from the memory 14 at the port 22, and the memory 13 is read at the port 23.
From the port 2
At 4, the packet is read from the memory 12.

With the above operation, access to the memory can always be started within one cycle, and the access wait time can be reduced. As a result, the data transfer delay time of the data buffer switch can be reduced. Each port is connected to the memory 11 → memory 12, the memory 12 → memory 13, the memory 1
Since the memory access is performed in a fixed order such as 3 → memory 14, memory 14 → memory 11, and the memory is accessed at a timing shifted by one time slot, access to the memory is started once. There is no need for a memory access wait time on the way.

FIG. 5 is an explanatory diagram for explaining a function when the memory access control unit 4 shown in FIG. 2 has a buffer management function for managing the memories 11 to 14 for each port. In FIG. 5, the buffer management function unit 5 inputs a buffer (memory) used by a packet transmitted through each of the ports 21 to 24 as a used buffer. After the used buffers are bundled by the multiplexer 51 in the buffer management function unit 5, they are distributed to the filters 61 to 64 according to an arbitrary setting, and are used as unused buffers in the storage units 71 to 74 for each port 21 to 24. Be managed. Therefore, it is possible to allocate an arbitrary area of the entire area of the memories 11 to 14 to each of the ports 21 to 24 by setting.

FIG. 6 is an explanatory diagram for explaining a function in a case where the memory access control unit 4 shown in FIG. 2 has a buffer management function for managing the memories 11 to 14 common to all ports. In FIG. 6, the buffer management function unit 5 inputs a buffer used by a packet transmitted through each of the ports 21 to 24 as a used buffer. The used buffer is stored in the multiplexer 5 in the buffer management function unit 5.
After being bundled by 1, the storage unit 7 is batched for all ports.
Is managed as an unused buffer. Therefore, there is no need to allocate a buffer per port, and the memory 11
14 can be used freely at each port, so that the memory can be used effectively and the memory use efficiency can be improved.

FIG. 7 is a diagram showing the timing when the data transfer rate (bandwidth) of each port of the switch shown in FIG. 2 is 1/2 of the data transfer rate of the memory. In the figure, 1A-4A, 1B-4B, 1C-4C, 1D-4D
Indicates packet data input from ports 21, 22, 23, and 24, respectively. Here, when the data transfer rate of each port is の of the data transfer rate of the memory, the four memories 11 to 14 are replaced with the two memories 11 and 12.
Can be reduced. Therefore, the four selectors 31
Can also be reduced to two selectors 31, 32.

In this case, the memory access control unit 4 returns an access response signal for the port to two ports simultaneously. The select signal to the selector is shifted by two time slots to be the select signal of the next memory. With this control, the memory 11 stores the packets 1A to 1D, 3A, 3B, 4A, and 4B, and the memory 12 stores the packets 2A to 2D, 3C, and 3B.
D, 4C, and 4D packets are stored. Therefore, it is possible to change the bandwidth of all ports depending on the number of memories to be accessed.

That is, for example, consider a case where data is input from the four ports 21 to 24 to the apparatus at a rate of 500 Mbps. In this case, considering the input of the packet data, 500 ports from four ports 21 to 24 respectively.
Since packets enter at a rate of Mbps, 2 Gbps (500 × 4 = 2000 Mbps) as a whole switch
ps). On the other hand, since the rate on the memory side has twice the rate of the port, 1 Gb
There is ps ability. Therefore, 500M for the entire switch
If there are four ports with a bps rate, it is sufficient to have two memories. Conversely, if there are four 1 Gbps rate memories, then up to eight 500 Mbps rate ports can be supported. Also, 1Gb
In the case of having two ps memories, four 500 Mbps rate ports and two 1 Gbps ports may be provided. Thus, the number of memories is determined not by the number of ports but by the bandwidth of all ports, and various combinations of the number of ports are possible within the range.

As described above, since the access to the memory from each port can always be started within one cycle, the memory access can be made constant regardless of the presence or absence of the access conflict. In the worst case where all ports read and transmit packet data received via one port and stored in the memory, the following access wait time can be guaranteed. That is, access wait time = (1 time slot time) × (number of ports−1) Time from when the first port starts reading until the last port finishes reading = (packet length) + (1
Time slot time) x (number of ports-1)

An arbitrary memory area can be allocated to each port. Further, the allocation of the memory area per port can be eliminated, and the memory can be used effectively. Further, the bandwidth of all ports can be changed depending on the number of memories to be accessed.

[0027]

As described above, according to the present invention, a plurality of memories for storing packets, a plurality of ports for accessing the memories, a selector for switching the connection between the ports and the memories, In a data buffer switch comprising a control unit for controlling a selector and connecting between a port and a memory, a write control unit and a read control unit are provided in the control unit, and the write control unit receives a packet received via the port. Is controlled so that each packet is distributed and written to each memory, and the read control means controls each packet distributed and stored in each memory to be read out individually and output to each port. Contention between ports is avoided when accessing the memory from the memory, so that the memory access waiting time can be reduced, and as a result, the data transfer delay of the device can be reduced. Possible to shorten the time. Further, the control unit is provided with a memory management unit that manages the memory for each port, and the memory management unit allocates an arbitrary area of the memory to the port based on a preset setting. Allocation is possible. In addition, since the control unit is provided with the memory management unit that manages the memory in common for each port, the use efficiency of the memory can be improved. Further, in the present data buffer switch, the bandwidth of all ports can be varied depending on the number of memories to be accessed, so that various combinations of the number of ports can be freely set within the range of the bandwidth.

[Brief description of the drawings]

FIG. 1 shows a first example of a data buffer switch according to the present invention.
It is a block diagram showing an embodiment.

FIG. 2 is a block diagram showing a second embodiment of the data buffer switch.

FIG. 3 is a diagram showing a data accumulation state of the data buffer switch.

FIG. 4 is a time chart showing an operation of a main part of the data buffer switch.

FIG. 5 is a diagram showing an example of a buffer management function of the data buffer switch.

FIG. 6 is a diagram showing another example of the buffer management function of the data buffer switch.

FIG. 7 is a timing chart showing the timing of changing the bandwidth of the data buffer switch.

FIG. 8 is a block diagram showing a configuration of a conventional device.

FIG. 9 is a diagram showing a data accumulation state of a conventional device.

FIG. 10 is a time chart showing the operation of the conventional device.

[Explanation of symbols]

4 memory access control unit 5 buffer management function unit
7, 71 to 74 ... store unit, 11 to 14 ... memory, 21
-24, ports, 31-34, selectors, 51, multiplexers, 61-64, filters.

Claims (4)

[Claims] 1. A plurality of memories for storing packets, a plurality of ports for accessing the memory, and a selector for switching connection between the port and the memory.
A data buffer switch comprising: a control unit that controls the selector to connect the port to a memory; a write control unit that writes a packet received via the port to each memory in the control unit in a distributed manner And a read control means for reading each packet written in a distributed manner in each memory and outputting the read packet to each port. 2. The control unit according to claim 1, wherein the control unit includes a memory management unit that manages the memory for each port, and the memory management unit allocates an arbitrary area of the memory to a port based on a preset setting. A data buffer switch, characterized in that: 3. The data buffer switch according to claim 1, wherein the control unit includes a memory management unit that manages the memory in common for each port. 4. The data buffer switch according to claim 1, further comprising a band changing unit that changes a band of all ports according to the number of the memories to be accessed.