JPH1188310A - Phase adjustment circuit for data and clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the phase adjustment circuit for data and a clock capable of securing a withstanding amount to jitter and wander and coping with duty degradation as well. SOLUTION: A delay part 1 outputs plural unit delay phase difference data. A phase judgement part 3 receives all the data, observes a position where the data change, and in the case that the change point of the data and the rise of the clock get close or the sample timing of the clock is at a duty degraded point, outputs signals for advancing or delaying a data phase corresponding to a state. A column counter part 4 and a row counter part 5 output counter signals for deciding a selection unit on the column side and on the row side of the selection circuit of a data selection part 2. The data selection part 2 selects the data for which the phase margin of the data and the clock is appropriate specified by the column counter and the row counter and outputs the data after adjustment. By a delay judgement part 6, delay data for judging and comparing the delay of a delay element are instructed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input data receiving circuit, and more particularly to an input data receiving circuit for receiving and processing input data having an arbitrary phase relationship with an input clock. The present invention relates to a data and clock phase adjustment circuit that can determine a phase relationship with a clock from a plurality of delay data generated by passing through an element and select and output data of a stable delay amount with a phase relationship with the clock.

[0002]

2. Description of the Related Art A conventional data and clock phase adjusting circuit has a method of adjusting a phase by determining a phase of data and a clock in the time for a phase adjustment within a cycle time. . At other times, the circuit does not adjust the phases of data and clock.

An example of a circuit having the above configuration is a "bit phase synchronization circuit" disclosed in Japanese Patent Application Laid-Open No. 4-293332.

In recent years, there has been an increasing demand for large-capacity, high-speed data processing. For this reason, it is necessary to perform multi-bit, high-speed data transmission between LSIs.

However, in the case of high-speed data transmission, the data cycle is short, so that the delay time among multi-bits varies greatly, making it difficult to reliably capture all data with a single-phase clock. Has become.

[0006]

A first problem of the conventional data and clock phase adjustment circuit is that a pattern for phase adjustment is required at regular intervals. Therefore, effective data cannot be transmitted during the phase adjustment, so that the effective bit rate is reduced. The reason is that there is a time for phase adjustment within a certain period of time, in which the phase of data and clock is determined and the phase is adjusted, and the phase of data and clock is not adjusted at other times This is because it is a circuit.

The second problem is that the resistance to jitter and wander is low. Depending on the amount of jitter or wander of both data and clock, the phase adjusted during the phase adjustment time may cause the phase relationship between clock and data to be lost, resulting in a loss of phase margin, and as a result, a problem that erroneous capture data may occur. It is expensive. The reason is that the data cycle is short in a region where the data rate is high, so that it is difficult to obtain a large phase margin between the data and the clock in the phase adjustment.

Furthermore, there is a problem in the stability of operation when the waveform of input data changes due to the deterioration of duty.
Originally, it is important to control the data selection delay position so that the clock phase does not become a point of data duty deterioration. However, even if such control is performed, some factor (such as initial setting or data and clock system switching) is required. Etc.), the clock phase may enter a point of duty deterioration. In this state, a bit error has occurred. In this case, the phase of the clock may not be able to escape from the point of the duty deterioration of the data in order to perform the phase control of the data and the clock by detecting the abnormal data change point existing due to the duty deterioration.

When the duty cycle of the input data is deteriorated, it is determined whether the sampling timing of the clock in the selected delay data is at the point where the duty is deteriorated. In the method proposed so far, in which the selection position of the delay data is forcibly changed and the operation of escaping from the point where the duty is deteriorated has been proposed, the circuit characteristics are such that the jitter tolerance is the delay value of the delay element. Depends on the absolute value. In general, when a delay is constituted by a semiconductor logic element, the delay value changes by a little less than three times due to a use environment and manufacturing variations of device parameters. For this reason, if the delay element is designed so as to increase the value of the delay so as to sufficiently satisfy the tolerance of the jitter, especially for high-speed data, the number of adjustment steps within one data rate decreases, and stable operation becomes difficult. . In addition, there is a problem that when the value of the delay is reduced, the tolerance of the jitter is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to suppress a decrease in an effective transmission rate due to a synchronization pattern for synchronizing phases in a data receiving circuit which captures input data by an input clock, and to ensure a tolerance against jitter and wander at a high rate. Another object of the present invention is to provide a data and clock phase adjustment circuit that can cope with duty deterioration.

[0011]

According to the present invention, there is provided an input data receiving circuit for receiving and processing input data having an arbitrary phase relationship with an input clock. A data and clock phase adjustment circuit that adjusts the phase and captures input data, wherein the delay phase of the input data is adjusted by a plurality of delay elements, and data of different delay amounts is captured by the input clock. A delay unit that outputs a plurality of unit delay phase difference data, and data that receives a plurality of unit delay phase difference data output from the delay unit and selects unit delay phase difference data having an appropriate phase margin between data and clock. Receiving the unit delay phase difference data output from the selection unit and the delay unit, and selecting the unit delay phase difference selected by the data selection unit Data and the unit delay phase difference data separated by one or more unit delay phase differences from the selected data, observe the position where the data changes, determine the relationship with the rising edge of the clock, and select A phase determination unit that outputs a signal to advance or delay the phase of the unit delay phase difference data, and a signal to advance or delay the data phase output from the phase determination unit, A column counter for outputting a counter signal for determining a selection unit of a column in the row direction of the selection circuit, and outputting a signal for advancing or delaying a data phase in the column direction; and a column direction output from the column counter. And a row counter for outputting a counter signal for determining a unit of row selection in the column direction of the selection circuit of the data selection unit in response to a signal indicating whether the data phase is advanced or delayed.

When the data change point approaches the rising edge of the clock, it is preferable that the phase determination section outputs a signal indicating whether the data phase is advanced or delayed according to the approach state. However, if the input data further has a duty deterioration, it is determined whether or not the clock sampling timing in the selected unit delay phase difference data is at the point where the duty is deteriorated. It is preferable to output a signal indicating whether to advance or delay.

The determination in the phase determination section may be performed by comparing the selected unit delay phase difference data with the unit delay phase difference data adjacent to the unit delay phase difference data by a phase difference of one delay element. May be executed by comparing the selected unit delay phase difference data with the unit delay phase difference data having a phase difference of one delay element and two delay elements in the unit delay phase difference data. The delay phase difference data is executed by comparing the unit delay phase difference data with the unit delay phase difference data having a phase difference of a plurality of delay elements in the unit delay phase difference data, and the number of delay elements between the unit delay phase difference data to be compared is determined. It may be changeable.

The data and clock phase adjustment circuit further measures the delay time of the delay element and changes the number of delay elements between the unit delay phase difference data to be compared with the selected unit delay phase difference data based on the result. It may include a delay determination unit that issues an instruction, and determines whether the unit delay phase difference data to be compared with the selected unit delay phase difference data is adjacent unit delay phase difference data with a phase difference of one delay element. The delay determining unit determines whether to select unit delay phase difference data having a phase difference of one delay element and two delay elements by unit delay time of the delay element of the delay unit. For example, unit delay phase difference data having a phase difference of one delay element and two delay elements is selected. If the delay time of the delay element is long, adjacent unit delay phase difference data is selected by a phase difference of one delay element. May be, the delay determining unit is capable of input of the test signal and the test control signal from the outside,
An arbitrary test signal may be output from the delay determination unit to the phase determination unit by controlling the test control signal.

In the data and clock phase adjusting circuit according to the present invention, the clock and data phase check is performed every time data changes by the above-described circuit configuration. Therefore, in the present invention, no special data for phase adjustment is required, and the data time for phase adjustment is unnecessary.

In the circuit configuration of the embodiment described later, the adjustment interval is about once every 500 CLK in the use example of the conventional circuit, but is not changed until the phase is actually changed from the data and clock phase check. Data capture + judgment +
Although 3CLK is required for the counter operation, the phase adjustment is performed at minute time intervals as compared with the related art.

As a result, according to the present invention, the amount of change in the jitter is determined by adding the time from the phase check of the data and the clock to the actual change of the phase to the change interval of the data and eliminating the phase margin of the data and the clock within the time. A jitter amount and a jitter frequency that do not change can be tolerated. This means that the jitter tolerance is improved as compared with the conventional example in which the tolerance must be provided for the accumulated jitter within the adjustment interval + wander amount.

For a phenomenon in which the phase shifts slowly and greatly, a multi-column multi-row unit delay flip-flop that generates a clock unit delay in the column direction (bit direction) in each unit delay phase difference data of the data selection unit. This is dealt with by the number of stages in the row direction (bit direction) of the group.

Further, in the present invention, the existence of the clock sampling point at the data duty deterioration point is automatically recognized and avoided. But operation becomes possible.

Further, in the present invention, the delay time of the delay element between the delay data to be compared with the selected delay data is the minimum time of the phase difference between the data change point and the clock during the normal operation, and the data change point and the clock change. Since the time of the phase difference is proportional to the jitter tolerance, the variation in the jitter tolerance can be reduced.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Next, a data and clock phase adjusting circuit according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an overall circuit diagram showing the configuration of a data and clock phase adjusting circuit according to a first embodiment of the present invention, and FIG. 2 is a data and clock phase adjusting circuit according to the first embodiment of the present invention. FIG. 3 is a circuit configuration diagram of a delay unit in the delay unit of the data and clock phase adjustment circuit according to the first embodiment of the present invention, and FIG. 4 is a circuit configuration diagram of the delay unit in the first embodiment of the present invention. FIG. 5 is a circuit configuration diagram of a phase determination unit according to the first embodiment of the present invention, FIG. 5 is a circuit configuration diagram of a detection circuit of the phase determination unit according to the first embodiment of the present invention, and FIG. 6 is a phase determination unit according to the first embodiment of the present invention. 7 is a circuit configuration diagram of the adjustment circuit, FIG. 7 is a circuit configuration diagram of an inset detection circuit of the phase determination unit according to the first embodiment of the present invention, and FIG. 8 is a delay determination unit according to the first embodiment of the present invention. FIG. 9 is a circuit configuration diagram of a column counter unit according to the first embodiment of the present invention, and FIG. Circuit diagram of the row counter part of the first embodiment, FIG. 11 is a circuit diagram of a data selection portion of the data and clock phase adjustment circuit according to the first embodiment of the present invention.

[1] Description of Configuration The configuration of the data and clock phase adjustment circuit according to the first embodiment of the present invention will be described with reference to the drawings. In addition,
Here, the vertical arrangement of the matrix of flip-flops is referred to as “row”, the horizontal arrangement is referred to as “column”, the vertical direction is referred to as “row direction”, and the horizontal method is referred to as “column direction”.

In the data and clock phase adjusting circuit according to the embodiment of the present invention, the clock input terminal 70 for inputting the input clock "CIN" and the data input terminal 71 for inputting the input data "DIN" are adjusted. Data "DOU
A data output terminal 72 for outputting "T" and input data "DIN" input from the data input terminal 71 are output from the multistage cascaded delay elements 11-1 to 11-12 without delay, 1-unit delay, ,..., 11 unit delays, each of which is separated into twelve pieces of data, and the separated data is received data first-stage flip-flop 10-
At time 0 to 10-11, the input clock “CIN” input from the clock input terminal 70 is input once, and “DA”
0 "," DA1 "," D0 "," Dl "," D2 ",
"D3", "D4", "D5", "D6", "D7",
A delay unit 1 that obtains unit delay phase difference data (hereinafter abbreviated as delay data) of “DA2” and “DA3” and outputs the data from unit delay phase difference data output terminals 123 to 134, and all of these 12 delay data And receives these data values and the counter output value of the column counter unit 4 to receive the input data “DIN” for the rising edge of the input clock “CIN” of the currently selected delay data (hereinafter abbreviated as “selected delay data”). ) Is determined from the relationship of the change position, and if the input data has duty deterioration,
It is determined whether or not the sample timing of the clock in the selected delay data is at a point where the duty is degraded, and the delay determination data of the delay determination unit 6 is input to change the interval to the delay data to be compared with the selected delay data. A phase determination unit 3 for outputting an "UP" signal for changing the selected delay data to delay data with a longer delay or a "DN" signal for changing the delay data to smaller delay data based on the result.
And the delay time of the delay element is determined, and as a result, if it is determined that the delay time is small, the phase determination unit 3 conversely increases the number of stages of the delay element to be compared with the selected delay data. Is large, a delay determination unit that outputs a signal instructing the phase determination unit 3 to reduce the number of delay elements to be compared with the selected delay data, and an “UP” signal or “ Receiving the “DN” signal, the column counter in the row direction is incremented by 1, incremented or decremented by one, and the phase determination unit 3 and the data selection unit 2
, And a “CUP” signal when receiving “UP” from the phase determination unit 3 when the value of the column counter is the maximum value, and “DN” from the phase determination unit 3 when the value of the column counter is the minimum value.
Column counter unit 4 that sends a “CDN” signal to the row counter unit 5 when receiving the “CUP” signal, “CD
In response to the "N" signal, a row counter unit 5 which sends the row counter value in the column direction one forward, one backward or no change to the data selection unit 2 and a matrix of flip-flops. The unit delay flip-flops 20-11 to 20- are configured to select the smaller and larger delay data in the column in the row direction and the data obtained by shifting each delay data by the clock in the row in the column direction.
14, 20-21 to 20-24, 20-31 to 20-3
4, 20-41 to 20-44, 20-51 to 20-54
, And selector circuits 21-1 to 21-5 and 23, and among the seven signals output from the delay unit 1, “D0”, “D1”, “D2”, “D3”, “ D
4 ”,“ D5 ”,“ D6 ”,“ D7 ”, the column counter value R <0-2> output from the column counter unit 4, and the row counter value C <output from the row counter unit 5 0-2>
, The delay data at which the change point of the input data with respect to the rise of the clock has a phase that does not cause a bit error is selected, and the data output terminal 7 is used as a “DOUT” signal.
2 and the flip-flops and counters in the delay unit 1, the data selection unit 2, the phase determination unit 3, the column counter unit 4, the row counter unit 5, and the delay determination unit 6 are initialized. And a reset input terminal 73 for inputting a reset signal “RSTB” for setting an initial value and outputting the signal as an “RSTB” signal.

[2] Description of Operation Next, the operation of the data and clock phase adjusting circuit according to the first embodiment of the present invention will be described with reference to the drawings. 1) Outline of operation: Delayed data “DA0”, “DA1”, “D0”, “D1”, “D” which are “outputs obtained by clocking data of different delay amounts” output from delay section 1
2 "," D3 "," D4 "," D5 "," D6 "," D
7 "," DA2 ", and" DA3 ", and determines the relationship between the phase of the selected delay data and the phase of the clock by the phase determination unit 3.
Monitor by As a result, if the phase margin between the selected delay data and the clock decreases, or if the input data has a duty degradation and the sample timing of the clock in the selected delay data is at a point where the duty has deteriorated, the delay determination unit is further reduced. 6, the interval until the delay data to be compared with the selected delay data is changed, and the instruction of the phase determination unit 3 (“UP”
Signal or “DN” signal), the selection circuit of the data selection unit 2 that operates according to the signal specified by the column counter unit 4 and the row counter unit 5 changes the delay data to be selected, thereby changing the data with respect to the clock. Increase the phase margin or escape from the point where duty is deteriorated. 2) Delay unit 1 (change in input data phase): (FIGS. 2 and 3)
(Refer to the data input terminal 120 “DIN”.)
IN "is the delay elements 11-1 to 11- having the configuration shown in FIG.
12 are input to a first-stage delay element 11-1 of a delay circuit in which multiple stages are connected in a row (Column) direction. The connection positions of the delay elements 11-1 to 11-12 (A, B, C,
D, E, F, G, H, I, J, K, L)
Received data first-stage flip-flops 10-0 to 10-11
The input clock “C” from the clock input terminal 121
LK ”and delay data“ DA0 ”and“ DA ”from the unit delay phase difference data output terminals 123 to 134.
1 "," D0 "," Dl "," D2 "," D3 "," D
4 "," D5 "," D6 "," D7 "," DA2 ",
Output as “DA3”. Delay element 11 until output
, The output data having different input data fetching phases can be obtained.

Note that the delay elements 11-12 are
The waveform of the output delay of 1-11 is transferred to the other delay elements 11-1 to 11-1.
This is a dummy element for making the output the same as 1-10. 3) Phase judging unit 3 (data and clock phase check): (see FIGS. 4 to 7) The phase judging unit 3 shown in FIG.
3. An inset detection circuit 35 is provided.

The detection circuit 31 shown in FIG.
, The column selection position data in the row direction of the column counter section 4, and whether the comparison delay data input from the delay determination section 6 should be changed to delay data with a larger delay difference or to smaller delay data. Is input, the selected delay data is compared with the preceding and following delay data. If there is a difference between the small delay data and UF = H, if there is a difference between the large delay data and DF = H, DF = H Output.

A selector 322 for inputting the results of EXORs 311 to 318 for comparing the delay data of the neighbors DA0 to D6 and selecting the data by the column selection position data in the row direction of the column counter unit 4, and a selector 322 for the DA1 to D7 A selector 323 that receives the results of EXORs 312 to 319 that compare the delay data of each other and selects it based on the column selection position data in the row direction of the column counter unit 4 and an EXOR 313 to that that compares adjacent delay data of D0 to DA2 A selector 324 for inputting the result of 320 and selecting by the column selection position data in the row direction of the column counter unit 4 and an EXOR 314 to 321 for comparing adjacent delay data D1 to DA3 and inputting the result of the column counter unit 4, a selector 325 for selecting by column selection position data in the row direction, an output of the selector 322 and an MS0 output of the delay determination unit. A force to AND326, selector 3
AND which inputs the output of the delay determination unit and the output of the delay determination unit MS0
327, an OR 328 that receives the output of the AND 326 and the output of the selector 323 and outputs “UF”,
27 and the output of the selector 324 are input and "DF"
And an OR 329 that outputs the same.

The selector 322 outputs a judgment on the difference between the delay data smaller by one delay element than the selected delay data and the delay data smaller by two delay elements, and the selector 323 judges the difference between the selected delay data and the delay data smaller by one delay element. And the selector 324 outputs a determination of the difference between the selected delay data and the delay data larger by one delay element.
Outputs a determination of the difference between the delay data larger by one delay element than the selected delay data and the delay data larger by two delay elements.
The change of the width of the delay time between the selected delay data and the delay data to be compared with one delay element or two delay elements is determined by the data of MS0 of the delay determination unit 6 and the ANDs 326 and 327.
This is realized by masking the outputs of the selectors 322 and 325.

OR3 of selector 323 and selector 322
The result of 28 is a result of detecting the presence or absence of a data change point within the delay time smaller by two delay elements from the selected delay data, and the OR 329 of the selector 324 and the output of the selector 325 is obtained.
Is a result of detecting the presence or absence of a data change point within the delay time larger by two delay elements from the selected delay data, and the input delay determination data MS0 of the delay determination unit 6 determines that the delay data smaller by two delay elements Difference judgment output and 2
When the output of the determination of the difference between the delay data with the large delay element is masked, the result of detecting the presence or absence of the data change point within the delay time of one delay element small or one delay element is detected. And signals UF and DF for the control circuit and the adjustment circuit.

The adjustment circuit 33 shown in FIG. 6 inputs UF and DF from the detection circuit 31 and EUP and EDN from the inset detection circuit 35, and outputs a counter up signal UP.
Alternatively, a counter down signal DN is output. UF, D
F, EUP, and EDN have a priority order, and EUP, E
DN has priority over UF and DF.

The input data UF and DF are fetched by flip-flops 334 and 335 and then output. UP = H
Alternatively, after the output of DN = H, the output of the phase determination unit 3 is stopped until the counter value of the subsequent stage changes and the selection delay data of the new selection position data is input. To stop. The mask signal for that purpose is NOR 342, flip-flops 343, 344, A
Created in ND345, UF, D in AND331 and 332
Mask the input of F.

The outputs EUP, E of the fit detection circuit 35
Since DN has priority over UF and DF, AND33
8 and 339 and the inverters 336 and 337 mask the output from the UF and DF.

In order to prevent the outputs of UP and DN from going high at the same time, DN is prioritized over UP by inverters 346 and AND347.

The indentation detection circuit 35 shown in FIG.
Detects the stuck state by inputting UF and DF from the detection circuit 31 and CUP and CDN from the column counter section 4, and detects a counter-up instruction signal E when the stuck state is detected.
It outputs UP or a counter down instruction signal EDN. When CUP = H or CDN = H, the inset detection is masked.

The inset detection circuit is provided with UF = H or D
F = H (= detection of difference between selected delay data and preceding and following delay data)
Judgment is made based on whether or not there is a difference in clock data values (= data has changed). If there is a change in the value of two consecutive clock data of the selected delay data input at UF = H or DF = H, there is no problem. If there is no change, it is determined that the clock phase of the selected delay data is at the point of duty deterioration. (Hereinafter, it is abbreviated as a stuck state). If it is determined that it is in the stuck state, EDN = H or EUP = H is output so as to forcibly change the selection delay data.

The input data UF is supplied to a flip-flop 352.
OR35 of data shifted by 1 clock and DF data
4 (= indicating whether there is a difference between the selected delay data and one or two delays next to the next delay data), and to the selector 351, the row position selection data of the delay data and the input delay data in the row direction And outputs the selected delay data, and outputs the presence / absence of a difference between two consecutive selected delay data by the flip-flop 353 and the EXOR 355. EXOR 356 compares the presence / absence of a difference between the selected delay data and the delay data of one delay adjacent thereto and the presence / absence of a difference between two consecutive delay data, and outputs the result to NANDs 357 and 358.

By inputting a UF value which is further delayed by one clock to the NAND 357, a result of detection of the stuck state is obtained. Further, the NAND 358 outputs a detection result of a stuck state by further inputting DF.

When a stuck state is detected at UF = H (= when there is a change point between the selected delay data and the small delay data), the selection delay data exceeds the change point phase of the data in the small delay data. Therefore, the NAND 357 issues a countdown instruction. On the other hand, if DF = H and the stuck state is detected, a count-up instruction is sent to NAN.
D358 comes out. The intrusion detection is performed three times in succession to escape from the intrusion state by exceeding the change phase of the data due to the duty deterioration. Therefore, OR359, AND360, counter 361, OR36
2. Three consecutive pulses are generated in the EDN by the NAND 363 and the OR 364. OR365, AND366,
Counter 367, OR368, NAND369, OR3
At 70, three consecutive pulses are created in the EUP.

After EDN = H or EUP = H, the values of the row counter and column counter at the subsequent stage change for four clock times, and the detection of jamming with the selected delay data at the new selected position data is performed. NOR 373 and flip-flops 374-37 to mask the inset detection
6 and AND377 to create mask data to mask the inset detection operation. Also, CUP = H or CD
When N = H, that is, when the row counter changes,
Since the continuity of the selected delay data is lost, it is necessary to mask the inset detection using the presence or absence of the difference in the selected delay data as a condition for detection. This mask also creates mask data with the NOR 371, the flip-flops 374 to 376, and the AND 377 to mask the inset detection operation. 4) Column counter unit 4: (see FIG. 9) As shown in FIG.
1, selector 402, OR403, 405, INV40
4, 410, 411, up / down counter 406, N
AND 407, 408, selector 409, AND 41
2, 413, a 3-bit up / down counter is configured, and can take values of 0, 1, 2, 3, 4, 5, 6, 7. Operated by a signal from the phase determination unit 3 and “U
“P” increases the value, and “DN” decreases the value. The initial value of the counter value by the reset signal is 4, and the counter value is sequentially changed from 4 → 5 → 6 → 7 → 0 → 1 → 2 → 3 → 4. Also, by "DN", 4 → 3 → 2 → 1 → 0 → 7 →
6 → 5 → 4 → 3. Based on the counter output, the unit delay amount of the column (Row) in the row direction of the output data selection circuit of the data selection unit 2 is determined, and the “CUP” and “CDN” signals are output to the row counter unit 5.

That is, the column counter section 4 mainly includes an up / down counter 406. R <0-2>
= L, L, L, DN = H and CDN = H, and instruct the row counter unit 5 to count down. Also, R <0
When −2> = H, H, H, UP = H and CUP = H, and instructs the row counter unit 5 to count up. 5) Row counter 5: (see FIG. 10) As shown in FIG.
01, OR 503, 505, INV 504, up / down counter 506, NAND 507, 508, and selector 509, a 3-bit up / down counter is configured, and can take values of 0, 1, 2, 3, 4. It operates according to the signal from the phase determination unit 3 and the state of the column counter unit 4. When the phase determination unit 3 is "UP" and the counter value of the column counter unit 4 is "7", the value is increased. D
When the value is "N" and the counter value of the column counter unit 4 is "0", the value is decreased. The initial value of the counter value is 2. The output of the row counter unit 5 determines the unit delay amount of a row (Column) in the column direction of the output data selection circuit of the data selection unit 2. 6) Data selection unit 2 (output data selection circuit): (FIG. 11)
As shown in FIG. 11, the data selection unit 2 includes the flip-flop groups “20-11, 20-12, 20-13, 20-1”.
4 "," 20-21, 20-22, 20-23, 20-
24 "..." 20-71, 20-72, 20-7
3, 20-74 "," 20-81, 20-82, 20-
83, 20-84 ", a group of signals" a1, b1...
g1, h1 "," a2, b2... g2, h2 ",
"A3, b3 ... g3, h3", "a4, b4 ...
.. g4, h4 "," a5, b5 ... g5, h5 "
, The row-direction delay selection signals “R0”, “R1”, which determine the selection unit of the column (Row) in the row direction of the column counter unit 4.
"R2" is used to select the row data column selection selector circuit 21-.
The delay data in the row direction is selected via 1, 21-2, 21-3, 21-4, 21-5. "R0", "R1",
“R2” is an output of the column counter unit 4 and is 0, 1, 2, 3,.
The values of 4, 5, 6, and 7 are shown. The output of the column counter 4 is 0
, Each row data column selection selector circuit 21 outputs “D0”
, Similarly, when it is 1, “D1”, when it is 2, “D2”,
Select "D3" for 3, "D4" for 4, "D5" for 5, 5, "D6" for 6, and "D7" for 7, as "DO1" to "DO5". Output to the row selection selector circuit 23.

The outputs of the flip-flops in each row in the column direction are delayed by one clock, and the column direction delay selection signals "C0" and "C1" for determining the selection unit of the column (row) in the column direction of the row counter unit 5. , "C2", the row delay data is selected via the row selection selector circuit 23.
“C0”, “C1” and “C2” are outputs of the row counter unit 5 and indicate values of 0, 1, 2, 3, and 4. Row counter 5
Is 0, the row selection selector circuit 23 outputs “DO
1 "," DO2 "when it is 1, and" DO "when it is 2.
"3", "DO4" at 3, and "DO5" at 4 are output as "DO". The output signal "DO" of the row selection selector circuit 23 is fetched by a clock at the row selection circuit output stage flip-flop 24, and is output from the phase-adjusted data output terminal 2507 as a "DOUT" signal. 7) Delay Judgment Unit: (See FIG. 8) The delay judgment unit 6 receives the clock signal and divides the frequency by the flip-flop 611 to generate cycle data that repeats H and L for each cycle. This periodic data is passed through the same delay elements 612 to 618 as those used in the delay unit 2, and each delayed data is
In steps 19 to 624, the data is fetched and output at the rising edge of the periodic data. That is, when the data passing through the delay element exceeds one cycle time, the output of the flip-flop becomes H, and it can be determined which delay element has reached one cycle time. In the delay determination unit 6, the initial value is set to L. MS0 is L →
It becomes H when the total delay time of the six delay elements 612 to 617 is smaller than the cycle time (= the outputs of the flip-flops 619 to 624 are All Low). In addition, MS0 goes from H to L because the delay element 612
616, which is longer than one cycle time (at least flip-flops 623 and 624 = H). The reason for changing the conditions that change between L → H and H → L is to prevent the operation of MS0 from becoming unstable. In addition, a protection function for keeping the output MS0 unchanged until the first delay time is determined after reset is realized by the level generator 625, the flip-flop 626, and the AND 630. Until the periodic signal (A0) rises after reset, (J) = L is output and the operation is performed so that MS0 does not change. The output delay determination data MS0 is L for a large delay and H for a small delay.

Next, the operation of the delay judging section 6 will be described with reference to the drawings. The H and L conditions of MS0 were determined as follows.

The conditions under which stable delay data that does not detect a data change point are always found in the present data and clock phase adjustment circuit will be described.

In the case of detection using two delay element times, two pieces of data before and after the selected delay data are compared with a total of four pieces of delay data. Therefore, it is sufficient that a delay time corresponding to five delay elements exists within one cycle time. In this case, since at least the four delay elements fall within the data period, a stable operating point exists. Therefore, the following control is performed. The initial state is
The condition of MS0 = L and the condition of MS0 = L → H are that the total delay time of the six delay elements is within one cycle.
The condition of = H → L is that the total delay time of the five delay elements is equal to or longer than one cycle time, thereby preventing the MS0 from frequently changing while satisfying the condition for finding a stable point.

FIG. 12 shows that the delay time of the delay element is small and MS
An example where 0 = L → H is shown. FIG. 12 is a time chart of the delay determination unit when the output delay determination data MS0 = L → H in the data and clock phase adjustment circuit according to the first embodiment of the present invention. The input CLK is frequency-divided by the flip-flop 611 to become periodic data (A0). (A0) in the H state immediately after the reset is performed by the delay element 612.
Through 617 to create delayed data of (B0-G0), fetched by flip-flops 619-624, and output (B1-G1). The output of the flip-flop in which the delay time from (A0) in the output of each delay element takes in the output of the delay element within the cycle of 1 CLK becomes L, and the output of the flip-flop becomes H from the point where it exceeds the cycle of 1 CLK. Becomes In FIG. 12, since the delay time of the delay element is small, even at the output of (G0), 1CLK
Of the flip-flop (B1 to B1)
G1) is All Low. When Time = 3, the protection signal (J) immediately after the reset of the delay determination unit 6 changes from L to H, and the delay determination unit 6 starts operating.

When the data of (B1 to G1) captured at the rising edge of (A0) at Time = 3 = All Low and MS0 = L, the output (H) of NOR627 becomes H.

At the rise of (A0) at Time = 5, M
S0 = L → H and (H) = H → L.

FIG. 13 shows that the delay time of the delay element is large and MS
An example in which 0 = H → L is shown. FIG. 13 is a time chart of the delay determination unit when the output delay determination data MS0 = H → L in the data and clock phase adjustment circuit according to the first embodiment of the present invention. The delay time of the delay element is larger than that of the example of FIG. 12, and when Time = 3, (F1, G1)
= H.

At the rising edge of (A0) of Time = 3, the data of (F1, G1) taken in at the rising edge of (F1, G1) = H, and the output (I) = H of AND628 when MS0 = H.

At the rise of (A0) at Time = 5, M
S0 = H → L and (I) = H → L. 8) Reset input terminal 63: reset signal "RSTB"
Is input, the flip-flops and counters in the delay unit 1, the data selection unit 2, the phase determination unit 3, the column counter unit 4, the row counter unit 5, and the delay determination unit 6 are initialized by the "RSTB" signal. And an initial value is set. 9) Operation Example An outline of the operation of the entire data and clock phase adjustment circuit will be described with reference to the drawings. FIG. 14 is a timing chart of the entire data and clock phase adjusting circuit according to the first embodiment of the present invention when MS0 = L.

The data input DIN is input to the delay unit 1, and data at each of the points A to L delayed by the delay elements 11-1 to 11-11 in the delay unit 1 is created. If you take in 10-0 to 10-11, DA
Delay data of <0-3> and D <0-7> is generated. Here, the current selection delay data is D from R <0-2> = 3.
3 is assumed.

In the phase determining section 3, since MS0 = L, D
Data to be compared with No. 3 are D2 and D4. Where D
For D3, D2 and D4 have the same data. In this state, it is determined that the state is stable, and the selection delay data is not changed.

Next, FIG. 15 shows the operation at the same DIN input as in FIG. 14 when MS0 = H. FIG. 15 is a block diagram of the entire data and clock phase adjusting circuit according to the first embodiment of the present invention.
It is a flowchart at the time of S0 = H.

In the phase determining section 3, since MS0 = H, D
The selection delay data of No. 3 is D3 and D2, D2 and D1, D3 and D4, and D4 and D5. Here, Time =
3, the difference between the data is detected by D2 and D1. Phase determination unit 3
The detection circuit 31 outputs UF = H, and the adjustment circuit 33
Outputs UP = H for one clock. The column counter unit 4 receiving UP = H counts up and R <0-2.
> = 4.

M detected in one delay element time in the example of FIG.
In the state where S0 = L, D3 is selected. That is, the relationship between the data and the clock in the selected delay state (F) is established. On the other hand, in the example of FIG. 15, D4 is selected at Time = 4 under the same input conditions as in FIG. That is, there is a relationship between the selected data of the delay state (G) and the clock. If the delay time of the delay element is the same, operating with two delay element detection, as can be seen by comparing (F) and (G), can operate the data change point away from the clock sample timing.

In the above-described embodiment of the present invention, an example has been described up to detection of two delay elements.
It is easy to perform detection at intervals longer than the delay element. Next, a data and clock phase adjusting circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG.
6 is an overall circuit configuration diagram showing a configuration of a data and clock phase adjustment circuit according to the second embodiment of the present invention, and FIG. 17 is a circuit configuration diagram of a delay determination unit according to the second embodiment of the present invention. is there.

The difference from the first embodiment is that the delay determination result MS0 is output to the terminal in FIG. 16, and a test signal TST and a test control signal TMS0 are added. The added TST and TMS0 are input to the delay determination unit 1006.

The delay judging unit 1 according to the second embodiment shown in FIG.
At 006, the TMS0 =
At the time of H, the data of TST is output to MS0 through, and when TMS0 = L, flip-flop 1632 is output to MS0.
Output data.

In this embodiment, MS0 can be controlled from the outside by a test signal TST. When the characteristics of an LSI incorporating this circuit are evaluated, MS0 is used.
By switching 0, the comparison of the fixed jitter characteristics can be performed.

[0060]

As described above, the first effect of the present invention is that no special data for phase adjustment is required, and the phase adjustment time is not required. The reason is that, as shown in FIG. 1, the phase check between the clock and the data is performed every time the data changes.

The second effect is that the present invention can tolerate a jitter amount and a jitter frequency that do not change until the phase margin between data and clock is lost within 3CLK + (data change interval = α) time. It is.
This is because in the conventional example, it was necessary to provide a tolerance against the accumulated jitter of 500 CLK time + wander amount.
Since LK + αCLK time is sufficient, it means that the jitter tolerance is improved. The reason is that, in the circuit configuration of the present invention, 3 CLK is required from the phase check of the data and the clock until the phase is actually changed, but in the use example of the conventional circuit, the adjustment is performed once every about 500 CLK. This is because the phase adjustment can be performed at minute time intervals as compared with that.

A phenomenon in which the phase shifts slowly and largely is dealt with by the number of stages in the column direction of the data selection unit. 1 CLK time per row (200 MHz)
Then, it has a tolerance of 5 nsec). In the embodiment, since the number of steps is 5 (= the center ± 2 steps), ± 2 CL
A phase shift of K time (10 nsec in the case of 200 MHz) can be handled.

The third effect is that operation becomes possible even when the duty of input data is deteriorated. The reason is that the present invention automatically recognizes and avoids the existence of the clock sampling point at the data duty deterioration point, and therefore does not cause stacking due to the duty deterioration.

The fourth effect is that the operation is fast. The reason is that the stuck-in state is always detected, and the judgment and the avoiding operation are automatically performed by only small-scale hardware.

The fifth effect is that it is possible to reduce the variation in the jitter tolerance of the phase adjustment circuit for the data and clock. The reason for this is that the data and clock phase adjustment circuit determines that the delay time of the delay element between the delay data to be compared with the selected delay data is the minimum time of the phase difference between the clock and the data change point during normal operation. This is because the time between the change point and the phase difference between the clocks is proportional to the jitter tolerance. When a delay circuit is constituted by only logic gates in an LSI, the dispersion of the delay time reaches a minimum and a maximum of about three times less. According to the present invention, the delay time of the delay element is determined, and if the delay time is small, the number of delay elements up to the delay data to be compared with the selected delay data is increased. This is because, by reducing the number of delay elements up to the data, variation in time between the delay data to be compared with the selected delay data is suppressed.

The sixth effect is that the cost of the LSI can be suppressed. The reason is that an analog circuit is not required to detect the stuck state or to determine the delay time of the delay element, and the whole circuit is realized by a logic circuit, so that it can be realized in a logic LSI. This is LS
Since it is not necessary to add an analog process to the I manufacturing, it is effective in reducing the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is an overall circuit configuration diagram showing a configuration of a data and clock phase adjustment circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a delay unit of the data and clock phase adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a delay element in a delay unit of the data and clock phase adjustment circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit configuration diagram of a phase determination unit according to the first embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a detection circuit of a phase determination unit according to the first embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of an adjustment circuit of the phase determination unit according to the first embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of an inset detection circuit of the phase determination unit according to the first embodiment of the present invention.

FIG. 8 is a circuit configuration diagram of a delay determination unit according to the first embodiment of this invention.

FIG. 9 is a circuit configuration diagram of a column counter unit according to the first embodiment of this invention.

FIG. 10 is a circuit configuration diagram of a row counter unit according to the first embodiment of this invention.

FIG. 11 is a circuit configuration diagram of a data selection unit of the data and clock phase adjustment circuit according to the first embodiment of the present invention.

FIG. 12 shows output delay determination data MS0 = in the data and clock phase adjusting circuit according to the first embodiment of the present invention.
9 is a time chart of the delay determination unit when L → H.

FIG. 13 shows output delay determination data MS0 = in the data and clock phase adjusting circuit according to the first embodiment of the present invention.
6 is a time chart of the delay determination unit when H → L.

FIG. 14 is a flowchart of the entire data and clock phase adjustment circuit when MS0 = L according to the first embodiment of this invention;

FIG. 15 is a flowchart of the entire data and clock phase adjustment circuit when MS0 = H according to the first embodiment of this invention.

FIG. 16 is an overall circuit configuration diagram illustrating a configuration of a data and clock phase adjustment circuit according to the second embodiment of this invention.

FIG. 17 is a circuit configuration diagram of a delay determination unit according to the second embodiment of this invention.

[Explanation of symbols]

1, 1001 delay unit 10-0 to 10-11 first stage flip-flop of received data 11, 11-1 to 11-12 delay element 110 to 115 delay NAND element 120 data input terminal 121 clock input terminal 122 reset input terminal 123 to 134 Unit delay phase difference data output terminal 2, 1002 Data selector 20-11 to 20-14 First column direction unit delay flip-flop 20-21 to 20-24 Second column direction unit delay flip-flop 20-71 to 20 -74 Seventh column direction unit delay flip-flop 20-81 to 20-84 Eighth column direction unit delay flip-flop 21-1 to 21-5 Row data column selection selector circuit 23 Row selection selector circuit 24 Row selection Circuit output stage flip-flops 2500 to 2507 Data "D0" before phase adjustment
“D4” input terminal 2508 Phase-adjusted data DOUT output terminal 2509 to 2511 Row direction delay selection signal “R0” to
"R2" input terminal 2512 to 2514 column direction delay selection signal "C0" to
"C2" input terminal 2515 Clock "CLK" input terminal 2516 Reset "RSTB" input terminal 3, 1003 Phase determination unit 31 Detection circuit 33 Adjustment circuit 35 Stuck detection circuit 311 to 321 355, 356 Logic circuit EXOR 322 to 325, 351 selector 326, 327, 331, 332, 338, 339, 3
45, 347, 360, 366, 377 Logic circuit A
ND 334, 335, 343, 344, 352, 353, 3
74 to 376 flip-flops 336, 337, 346, logic circuit INV 328, 329, 340, 341, 354, 359, 3
62, 364, 365, 368, 370 Logic circuit O
R 342, 373 Logic circuit NOR 357, 358, 363, 369 Logic circuit NAND 361, 367 Counter 371, 372 Level generator 4, 1004 Column counter unit 401 Level generator 402, 409 Selector 403, 405 Logic circuit OR 404, 410 411 Logic circuit INV 406 Up / down counter 407, 408 Logic circuit NAND 412, 413 Logic circuit AND 5, 1005 Row counter section 501 Level generator 503, 505 Logic circuit OR 504 Logic circuit INV 506 Up / down counter 507, 508 Logic circuit NAND 509 selector 6, 1006 delay determination unit 611, 619 to 624, 626, 632, 1611,
1619-1624, 1626, 1632 Flip-flops 612-618, 1612-1618 Delay element 625, 1625 Level generator 627, 1627 Logic circuit NOR 628, 630, 1628, 1630 Logic circuit AN
D 629, 1629 Logic circuit OR 631, 1631, 1633 Selector 70, 1070 Clock “CIN” input terminal 71, 1071 Data “DIN” input terminal 72, 1072 Data “DOUT” output terminal 73, 1073 Reset “RSTB” input terminal

Claims (9)

[Claims] 1. An input data receiving circuit for receiving and processing input data having an arbitrary phase relationship with an input clock, wherein the input data corresponding to the input clock is passed through a plurality of delay elements to generate a plurality of delay amounts. A data and clock phase adjustment circuit that determines a phase relationship with a clock from data and selects and outputs data of a stable delay amount with a phase relationship with the clock, wherein the delay phase of input data is A delay unit that captures data of different delay amounts generated by passing through a plurality of unit delays with an input clock and outputs a plurality of delay data, and receives a plurality of the delay data output from the delay unit. A data selection unit for selecting delay data having an appropriate phase margin between data and a clock; and a plurality of the delay data output from the delay unit. Receive all of the data, observe the position where the data changes, determine the relationship with the rising edge of the clock, and select the delay data to be selected with a larger or smaller delay A phase determination unit that outputs an instruction signal as to whether to keep the current delay data, and receiving an instruction signal output from the phase determination unit, selecting a column in a row direction of a selection circuit of the data selection unit A column counter unit that outputs a counter signal that determines a unit, and outputs a signal that is output from the phase determination unit and that determines a change in a selection position in a column direction based on the instruction signal and the counter signal; A row counter unit, which receives a signal instructed to change the selection position in the column direction and outputs a counter signal for determining a selection unit of a row in the column direction of the selection circuit of the data selection unit. The phase adjustment circuit of the data and the clock, characterized in that. 2. When the phase determination unit determines that the selected change point of the delay data is close to the rising edge of the clock, the phase determination unit has a more stable phase relationship with the clock according to the state of the proximity. 2. The data and clock phase adjusting circuit according to claim 1, wherein an instruction signal for changing to the delayed data is output. 3. The phase determining section further determines whether or not the sampling timing of the clock in the selected delay data is at a point where the duty is deteriorated when the input data further has a duty deterioration. And outputting an instruction signal indicating whether the selected delay data has a larger delay amount, a smaller delay amount, or the current delay data. The data and clock phase adjustment circuit according to 1. 4. The phase determination unit according to claim 2, wherein the determination is performed by comparing the selected delay data with the delay data adjacent to the delay data with a phase difference of one delay element. 3. The data and clock phase adjustment circuit according to 3. 5. The determination in the phase determination unit is performed by comparing the selected delay data with the delay data having a phase difference of one delay element and two delay elements in the delay data. 4. The data and clock phase adjustment circuit according to claim 2 or claim 3. 6. The determination in the phase determination unit is based on a comparison between the selected unit delay phase difference data and the unit delay phase difference data having a phase difference of a plurality of delay elements in the unit delay phase difference data. 4. The data and clock phase adjusting circuit according to claim 2, wherein the number of delay elements between the unit delay phase difference data to be executed and compared is changeable. 7. The data and clock phase adjusting circuit further measures the delay time of the delay element, and compares the delay time with the unit delay phase difference data selected based on the measurement result. 7. The data and clock phase adjustment circuit according to claim 6, further comprising a delay determination unit that issues an instruction to change the clock. 8. The unit delay phase difference data to be compared with the selected unit delay phase difference data may be the adjacent unit delay phase difference data with a phase difference of one delay element, Whether to select the unit delay phase difference data having a phase difference for the delay element, the delay determination unit determines the magnitude of the unit delay time of the delay element of the delay unit,
If the delay time is small, the unit delay phase difference data having a phase difference of one delay element and two delay elements is selected,
8. The data and clock phase adjusting circuit according to claim 7, wherein if the delay time of the delay element is long, the adjacent unit delay phase difference data is selected with a phase difference of one delay element. 9. The delay judging unit can receive a test signal and a test control signal from the outside, and control the test control signal to transmit any test signal from the delay judging unit to the phase judging unit. 8. The data and clock phase adjusting circuit according to claim 7, which can output.