JPH1188303A - Bit error rate measuring instrument - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a consideration of a factor in an error rate generation simple by measuring the number of generation rates of periodic error as a spectrum for a frequency. SOLUTION: When a bit error rate of a measured object 20 is measured, a memory 80 reads in values of a clock counter 40 and an error counter 50 after storing an output signal of a clock counter 40 and an output signal of an error counter 50 as time sequence data of an error status, eliminates the number of error statuses by a clock counter value by an operation processor 70 and obtains the bit error rate. At this time, it is possible to simply analyze a generation cause of a periodic error of the measured object 20 by performing a Walsh transformation operation, obtaining the number of each periodic error generation rate for an inverse number of periods T1 and T2 as a Walsh spectrum within a measurement bit length, and displaying the result on a display means 90.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error rate measuring device capable of measuring the frequency of occurrence of a periodic error.

[0002]

2. Description of the Related Art A conventional bit error rate measuring device will be described with reference to FIG. As shown in the block diagram of FIG. 4, the bit error rate measuring device includes a test pattern generator 11, a modulator 12, a comparator 30, a clock counter 40, an error counter 50, a comparator 60, and an arithmetic processor. 70. Then, the bit error rate of the measured object 20 is measured. The measurement target 20 is, for example, a PDC in a mobile phone.
/ PHS etc.

First, an outline of the operation will be described. The test signal is obtained by modulating a test pattern generated by a test pattern generator 11 with a modulator 12 and applying a modulated wave 100 to the measured object 20 as a test signal. The demodulated data 200 demodulated by the device under test 20 and the transmission clock 300 are reproduced. Then, the test pattern and the demodulated demodulated data 200 are transmitted by the transmission clock 300.
The error is detected by comparing with the comparator 30 in synchronism with the above.

Next, details of each constituent block and operation will be described. The test pattern generator 11 is, for example, 960
Generates a pseudo-random test pattern at a data rate of 0 bps.

Here, the pseudo random test pattern is
It is a pattern that has periodicity but is partially random. For example, a pseudo-random test pattern that can be generated by using a seven-stage shift register generates a pattern having a bit length of 10 ⁷ -1 excluding the case of all 0s.

[0006] The modulator 12 is a quadrature modulator, and sets H (high) to +
This is a modulation method in which 1, L (low) is made to correspond to -1 and information is transmitted by switching the phase of a carrier wave. For example, there is a π / 4 shift QPSK as a modulation scheme, and an 8
A frequency in the 00 MHz band is used.

[0007] Then, in the DUT 20, the modulated wave is detected and the transmission clock is reproduced and output from the demodulated data and the data rate of the test pattern. Further, the comparator 30 compares the demodulated data and the test pattern bit by bit in synchronization with the transmission clock, and outputs an error signal to the error counter 50 when they are different.

The clock counter 40 counts a transmission clock. The error counter 50 increments the counter each time an error occurs.

When the value of the set measurement bit length becomes equal to the count number of the clock counter 40, the comparator 60 notifies the arithmetic processor of the end of data acquisition.

After receiving the notification of the end of the data acquisition, the arithmetic processor 70 reads the values of the clock counter 40 and the error counter 50 and calculates the bit error rate of the following equation (1). Bit error rate = value of error counter / value of clock counter ... (1)

In general, if the measurement bit length is set to be long, the reproducibility of the bit error rate is improved, but the data acquisition time is lengthened. Here, the term "reproducibility" refers to the magnitude of data variation when repeatedly tested under the same test conditions. For example, when a pattern with a data rate of 9600 bps is fetched with a measurement bit length of 1000 bits, the time is 104 ms, and when data is fetched with 1 million bits, the time is 104 sec.

However, even if the reproducibility is improved by increasing the measurement bit length, it is hard to provide a clue for examining the cause of the error of the measured object 20.

That is, it is difficult to understand what the characteristics of the bit error rate generated by the measured object 20 are.

[0014]

As described above, it is possible to improve the reproducibility of the error of the measured object 20. However, it is possible to obtain data on the characteristics of the error generated by the measured object 20. Therefore, there is a practical inconvenience in which it is difficult to consider the cause of the bit error rate. Accordingly, the present invention has been made in view of such a problem, and an object of the present invention is to provide a bit error rate measuring device capable of measuring the frequency of occurrence of a periodic error generated by an object to be measured.

[0015]

That is, the first object of the present invention to achieve the above object is to provide a bit error rate measuring device characterized in that the frequency of occurrence of a periodic error can be measured as a spectrum with respect to frequency. It is a gist.

A second aspect of the present invention to achieve the above object is to provide a comparator for logically comparing a test pattern and demodulated data to be measured in synchronization with a transmission clock;
A clock counter that counts a transmission clock, a comparator that notifies the end of data acquisition when the count number of the clock counter matches the measurement bit length,
An error counter that counts errors; a memory that stores error data of the error counter using an output signal of the clock counter as an address; an arithmetic processor that reads data from the memory and performs a Walsh transform operation; And a display means for displaying a calculation result of the bit error rate measuring device.

Further, a third aspect of the present invention, which has been made to achieve the above object, is to provide a measurement bit length as a power of two,
The gist of the bit error rate measuring device according to the second aspect of the present invention is to notify the completion of data acquisition to the arithmetic processor when the count number of the clock counter matches with the comparator.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. As shown in the block diagram of FIG. 1, the bit error rate measuring device of the present invention comprises a test pattern generator 1
1, a modulator 12, a comparator 30, a clock counter 40, an error counter 50, a comparator 60,
A memory 80 and a display means 90 are added to the conventional configuration of the arithmetic processor 70. Then, the bit error rate of the measured object 20 is measured.

Next, each component block and operation will be described. Here, the arithmetic processor 70, the memory 80,
The operation other than the display means 90 is the same as the conventional operation, and the description is omitted.

The memory 80 stores the output signal of the error counter 50 as time-series data of the error status using the output signal of the clock counter 40 as an address.
After receiving the notification of the end of the data acquisition from the comparator 60, the clock counter 40 and the error counter 50
Is read, and the arithmetic processor 70 calculates the bit error rate of the following equation (2). Bit error rate = error status number in memory / clock counter value (2) As shown in FIG. The case with data is represented as a vertical axis, and is displayed as a characteristic diagram of the occurrence of an error. For example, the characteristic of the error shown in FIG.
It is assumed that a plurality of errors having a period T1 as shown in FIG. 2B and a plurality of errors having a period T2 as shown in FIG. In this case, it is not known from the characteristic diagram of FIG. 2A whether or not there is a periodicity error and what kind of periodicity error is.

Therefore, the arithmetic processor 70 has the memory 8
The data of 0 is read and the Walsh transform is calculated. Here, the Walsh transform is a transform system that simplifies the Fourier transform, and an analysis system using the Walsh transform is disclosed in Japanese Patent Application Laid-Open No. 57-700, “Speech recognition device”. Also, the Walsh function has its element +
Since there are only 1 and −1, the Walsh transform is suitable for calculating a digital signal.

The error status in the memory 80 corresponds to a state without an error as -1 and a state with an error as +1 to perform a Walsh transform in the range of the measured bit length to obtain a Walsh spectrum. Can be

Therefore, the Walsh spectrum is shown in FIG.
As shown in FIG. 2A, from the error of FIG. 2A, the reciprocal of the period T1 and the period T2, that is, the frequency 1 / T1 and the frequency 1 /
The respective periodic error occurrence frequencies for T2 and T2 are obtained. Further, by displaying this result on a display as a display means 90, for example,
The cause of the periodicity error can be easily analyzed.

By setting the measurement bit length to a power of two, a high-speed Walsh transform can be performed, so that the calculation time can be reduced.

[0025]

The present invention is embodied in the form described above and has the following effects. That is,
Since the periodicity error can be measured as the reciprocal of each period, that is, the frequency of occurrence of the periodicity error with respect to the frequency,
There is an effect that data on what is the feature of the error generated by the measured object is obtained. Therefore, there is an effect that it is easy to consider the factor of the occurrence of the bit error rate of the measured object.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bit error rate measuring device of the present invention and an object to be measured.

FIG. 2 is a characteristic diagram of occurrence of an error with respect to an address of a clock counter.

FIG. 3 is a graph showing frequency error occurrence frequency characteristics with respect to frequency.

FIG. 4 is a block diagram of a conventional bit error rate measuring device and an object to be measured.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Test pattern generator 12 Modulator 20 DUT 30 Comparator 40 Clock counter 50 Error counter 60 Comparator 70 Arithmetic processor 80 Memory 90 Display means 100 Modulation wave 200 Demodulation data 300 Transmission clock

Claims (3)

[Claims] 1. A bit error rate measuring device capable of measuring a frequency of occurrence of a periodic error as a spectrum with respect to a frequency. 2. A comparator for logically comparing a test pattern and demodulated data to be measured in synchronization with a transmission clock, a clock counter for counting the transmission clock, a count number of the clock counter, a measurement bit length, A comparator that notifies the end of data acquisition when the values match, an error counter that counts errors, a memory that stores error data of the error counter using an output signal of the clock counter as an address, and reads data from the memory. A bit error rate measuring device, comprising: an arithmetic processor for performing a Walsh transform operation in (1); and display means for displaying an arithmetic result of the arithmetic processor. 3. The bit error rate measuring device according to claim 2, wherein when the measured bit length as a power of 2 and the count number of the clock counter coincide with each other in the comparator, the end of data acquisition is notified to the arithmetic processor.