JPH1188049A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit which can be integrated and also a divider frequency circuit which can be driven at a low voltage level. SOLUTION: An oscillation circuit includes the transistors TR Q1 to Q10 and the bias resistors R1 to R4, r1 and r2 which controls the amplification factors of the TR Q1 to Q10. When the gate voltage of the TR Q1 rises and lowers, the feedback control is performed to lower and raise the gate voltage respectively. A divider circuit includes a transconductance part and a divider part, and the connection of three or more TRs is inhibited between a power voltage terminal Vcc and a ground terminal at both transconductance and divider parts. Thus, the power voltage can be set at a low level and accordingly the power consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for integrating an oscillation circuit and a frequency dividing circuit on a semiconductor substrate.

[0002]

2. Description of the Related Art Oscillation circuits can be classified by circuit type.
Representative examples include a Colpitts oscillator, a Hartley oscillator, and a multivibrator shown in FIG. These oscillation circuits generally include an active element for amplifying a signal and a passive element such as an inductor or a capacitor for determining an oscillation frequency.

In recent years, in the field of semiconductor integrated circuits for analog communication, voltage controlled oscillators (VCOs) have been used in local oscillators at the front end of analog receivers and reference signal generators in PLL (Phase Locked Loop) circuits. : Voltage
Controlled Osccilator) and current controlled oscillator (CCO: Cu
rrent Controlled Oscillator) is often used.

[0004] Recent advances in semiconductor integrated circuit manufacturing technology tend to reduce the size and integration of electronic circuits as a whole. Conventionally, analog semiconductor integrated circuits for high frequencies have been mainly integrated based on compound semiconductors.However, advances in microfabrication technology have made it possible for silicon semiconductors to operate as high as compound semiconductors. ,
In recent years, high-frequency integrated circuits have often been formed on silicon substrates. As a result, the circuit scale can be significantly reduced as compared with a conventional high-frequency circuit configured by combining discrete elements.

For example, taking the configuration of the front end portion of a receiver as an example, an example in which a low noise amplifier, a frequency mixer, and an intermediate frequency amplifier in the front end portion are integrated into an IC with the miniaturization of transistors has already been disclosed. (MW
E'95 Microwave Workshop Digest p.380-385).

[0006]

However, on the other hand, downsizing of the oscillator in the front end portion is delayed as compared with other circuits, and a considerable mounting area is required. One of the reasons why the downsizing of the oscillator is delayed is that it is technically difficult to miniaturize an inductor or a capacitor which is a part of a passive element constituting the oscillator.

At present, an oscillator used inside a receiving circuit generally uses a capacitor called a voltage variable capacitance element (commonly called a varicap) for the purpose of externally controlling an oscillation frequency. However, at present, the varicap also has a large area occupied by the substrate similarly to the above-described passive element, and is difficult to integrate, and is almost always provided externally. As described above, there are several factors that hinder downsizing of the oscillator, and it is often difficult to easily solve the problem.

Therefore, in order to reduce the chip size of a semiconductor integrated circuit, particularly an analog semiconductor integrated circuit, a circuit design technique that minimizes the use of passive elements such as inductors and capacitors is established, or passive elements can be used. It is desirable to reduce the size as much as possible.

However, miniaturization of the latter passive element is technically difficult. For example, the inductor has the largest element value (unit: H) currently realized on the silicon integrated circuit due to the influence of the loss with the substrate, the parasitic resistance of the wiring, and the like.
(Henry)) was introduced in 1990 by Nguyen and Meyer and others.
J. Solid-State Circuits vol.25, No.4, pp.1028-1031
9.7nH is the highest at present, and no further examples have been reported. Depending on the frequency band used, it is still not enough to achieve up to 10nH, and depending on the application used, some oscillators require an inductor of several μH. Must use an external inductor.

Further, from the standpoint of manufacturing an integrated circuit, extra masks, steps, and an Al wiring layer are required to form an inductor and a capacitor in the integrated circuit, which increases the manufacturing cost.

As described above, in order to reduce the size of the oscillator, it is desirable to use a circuit in which the number of elements such as inductors and capacitors used in the circuit is as small as possible.

On the other hand, an oscillator is often used in combination with a frequency divider. For example, in a PLL circuit, a reference oscillation signal and a PLL output signal are input to separate frequency dividers, respectively, and control is performed so that the frequency and phase of the output of each frequency divider match. For this reason, when integrating the oscillator, it is desirable to integrate the frequency divider together.

[0013] As shown in FIG.
Type flip-flops (for example, IEEE Journal of Solid State Circuits. Vol. 27,
No.12. December 1992, or IEEE Journal of Solid
State Circuits. Vol. 29, No. 10. October 1994). The reason for using a T-type flip-flop is that it is considered that stable circuit operation is guaranteed.

The frequency dividing circuit shown in FIG. 20 includes a clock input unit 51 to which a clock signal is input, a hysteresis unit 52 whose logic is inverted according to the clock signal, and a hysteresis unit 5.
Constant current source 5 for controlling the current flowing through the transistors in 2
3, a load unit 54 for determining the amplitude level of the output signal,
An impedance conversion unit 55 that performs impedance conversion.

In recent years, as portable devices such as cellular phones and notebook computers have become widespread, the power supply voltage of semiconductor integrated circuits has tended to decrease in order to reduce power consumption. It is required to work. For example, consider the power supply voltage level of the conventional frequency divider shown in FIG.

It is desirable that the transistors in the clock input section 51, the hysteresis section 52, and the constant current source 53 shown in FIG. 20 be operated (not saturated) in the active region. This is because when the transistor is saturated, the cutoff frequency fT decreases, and it becomes difficult to operate the circuit at high speed. Generally, the voltage between the base and the emitter required for turning on the transistor is 0.8 V. Therefore, in order to operate the transistor in the active region, the voltage between the collector and the base needs to be (-0.2 V) or more. When this condition is converted into a collector-emitter voltage VCE, the equation (1) is obtained.

VCE = VBE + VCB = 0.8 + (− 0.2) = 0.6V (1) From the equation (1), in order to operate the transistor in the active region, the voltage VCE between the collector and the emitter of the transistor must be set to 0.
Must be at least 6V.

The constant current source 53 shown in FIG. 20 has a stabilizing resistor for stably operating the transistor.
With this resistor, to suppress the increase in bias current,
It is desirable to consume a voltage of at least about 0.2V.
Further, in order to operate the transistor at high speed, it is desirable to set the voltage amplitude of the load section 54 to about 0.3V.

For example, the document "T. Akiyama et. A1:" 1.8 GHz
low power & low voltage silicondual modulus presc
aler ", in Proc. VLSI Circuits Symp., 1987"
To operate the flip-flop at high speed, the load unit 54
It is described that it is desirable to set the voltage amplitude of the signal to 0.3 V.

Taking the above conditions into account, FIG.
Minimum power supply voltage V for stable operation of frequency divider circuit of 0
cc is represented by the following equation (2).

Vcc = (voltage of resistance in constant current source 53) + 3 × (collector-emitter voltage VCE required for operating the transistor in the active region) + (voltage consumed by load unit 54) = 0.2 + 3 × 0.6 + 0.3 = 2.3 [V] (2) Generally, below the power supply voltage Vcc expressed by the equation (2),
Stable operation is not guaranteed. The power supply voltage Vcc is
As a method of further lowering the voltage value expressed by the equation, it is conceivable to lower the consumption voltage of each part in the frequency dividing circuit of FIG. 20, but for example, it is inserted into the emitter terminal of the transistor constituting the constant current source 53. If the resistance is reduced, the current flowing through the constant current source 53 fluctuates due to variations in the manufacturing process of the integrated circuit, and the characteristics change.

When the voltage applied to the load section 54 in the frequency dividing circuit shown in FIG. 20 is reduced, the operating speed of the T-type flip-flop is reduced. Further, since the voltage at which the transistor is saturated fluctuates due to a manufacturing process or the like, it is desirable to supply a voltage with some allowance.

As described above, as long as the circuit configuration as shown in FIG. 20 is used, there is a problem that the power supply voltage level can be reduced only to a certain extent and the power consumption cannot be reduced so much.

The present invention has been made in view of the above points, and has as its object to stably perform an oscillating operation without using an inductor or a capacitor, and to facilitate integration on a semiconductor substrate. To provide a simple oscillation circuit.

Another object of the present invention is to configure a frequency dividing circuit capable of driving at a low voltage.

[0026]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises first and second transistors which are emitter-coupled or source-coupled, and wherein the second transistor is connected to the second transistor.
A third transistor whose base terminal voltage or gate terminal voltage changes according to a collector terminal voltage or a drain terminal voltage of the transistor, a first bias circuit for setting an amplification factor of the first transistor, 2
A second bias circuit for setting the amplification factor of the transistor, and a third bias circuit for setting the amplification factor of the third transistor, wherein the base terminal voltage or the source terminal voltage of the first transistor is , The voltage is controlled according to the collector terminal voltage or the drain terminal voltage of the third transistor, and the base terminal voltage or the source terminal voltage of the second transistor is controlled according to the collector terminal voltage or the drain terminal voltage of the first transistor. And outputs an oscillation signal from the collector terminal or the drain terminal of the third transistor.

The invention of claim 1 will be described with reference to FIG. 2, for example. "First to third transistors" correspond to transistors Q1 to Q3, and "first to third bias circuits" correspond to biases, respectively. It corresponds to the resistors R1 to R3.

The invention of claim 2 will be described with reference to FIG. 2, for example. The "impedance element" corresponds to the bias resistors R1 to R3, and the "first bias control circuit" corresponds to the bias control circuit 10.

According to a third aspect of the present invention, the first to eighth transistors, a first bias circuit for setting an amplification factor of the first and fifth transistors, and an amplification of the second and fourth transistors are provided. A second bias circuit for setting the amplification factor; a third bias circuit for setting the amplification factor of the third and seventh transistors; and a fourth bias for setting the amplification factor of the sixth and eighth transistors. And an emitter terminal or a source terminal of the first, second, fourth and fifth transistors is connected to each other, and an emitter terminal or a source of the third, sixth, seventh and eighth transistors is connected to the first, second, fourth and fifth transistors. The terminals are connected to each other, and the base terminal voltage or the source terminal voltage of the first and eighth transistors is equal to the collector terminal voltage or the collector terminal voltage of the third and seventh transistors. Controlling the base terminal voltage or the source terminal voltage of the second and sixth transistors according to the collector terminal voltage or the drain terminal voltage of the first and fifth transistors; The base terminal voltage or the source terminal voltage of the fourth and seventh transistors is controlled according to the collector terminal voltage or the drain terminal voltage of the sixth and eighth transistors, and the base terminal voltage of the third and fifth transistors is controlled. Voltage or source terminal voltage
Oscillation signals are output from the collector and drain terminals of the third and sixth transistors, respectively, being controlled in accordance with the collector and drain terminal voltages of the second and fourth transistors.

The invention according to claim 3 will be described with reference to FIG. 1, for example. "First to eighth transistors" are transistors Q1 to Q8, respectively, and "first to fourth bias circuits" are bias resistors. Corresponds to R1 to R4.

The invention of claim 4 will be described with reference to, for example, FIG. 1. "Impedance element" corresponds to bias resistors R1 to R4, and "first bias control circuit" corresponds to bias control circuit 10.

The fifth and sixth aspects of the present invention will be described with reference to FIG. 11, for example. "Fifth and sixth bias circuits" correspond to the bias resistors R5 and R6, respectively.

If the invention of claim 7 is explained with reference to FIG. 11, for example, the "second bias control circuit" corresponds to the bias control circuit 10 '.

The invention of claim 8 will be described with reference to, for example, FIG. 2. The "ninth transistor" corresponds to the transistor Q9.

The ninth and tenth transistors correspond to the transistors Q9 and Q10, respectively.

The tenth aspect of the present invention will be described with reference to, for example, FIG. 1. In FIG. 1, the "first to tenth transistors" are all constituted by bipolar transistors.

The invention according to claim 11 will be described with reference to, for example, FIG. 7. In FIG. 7, "the first to tenth transistors" are all constituted by MOS transistors.

The invention according to claim 12 will be described with reference to, for example, FIG. 9. In FIG. 9, the "first to fourth bias circuits" are constituted by diode-connected MOS transistors.

According to a thirteenth aspect of the present invention, there is provided a semiconductor integrated circuit having a frequency divider for outputting a frequency-divided signal obtained by dividing an externally input clock signal by an integer multiple, wherein the clock signal and its inverted signal are A complementary clock output unit that outputs a complementary signal according to a voltage difference, the frequency divider outputs the frequency-divided signal based on the complementary signal, and the frequency divider and the complementary clock output unit include: As the power supply voltage, the first
And the second voltage are supplied, the frequency divider and the complementary clock output unit each include a plurality of transistors functioning as active elements, and the transistors are connected in series between the first and second voltage terminals. Are reduced to two or less.

The invention according to claim 13 will be described with reference to, for example, FIG. 13. In the following description, the "frequency divider" is assigned to the frequency divider 22 and the "complementary clock output" is assigned to the transconductance unit 21.
The “first voltage” corresponds to the power supply voltage Vcc, and the “second voltage” corresponds to the ground voltage.

The invention according to claim 14 will be described with reference to FIG. 13, for example. "Transistors functioning as active elements" include transistors Q21 to Q27, Q29, and Q30 to 43.
"Impedance element" is resistance R21, R22, R29, R3
0, R32, and R33 have a "bias circuit" (Q29, R2
6), (Q25, R23), (Q26, R24), (Q27, R2
5), (Q34, R31), (Q39, R34), (Q42, R3)
5) and (Q43, R36) respectively.

The invention of claim 16 will be described with reference to FIG. 13, for example.
The “constant current source” corresponds to the constant current source 25, and the “first impedance converter” corresponds to the impedance converter 24.

The invention of claim 18 will be described with reference to FIG. 13, for example. The "second impedance converter" corresponds to the transistors Q40 to Q43 and the resistors R35 and R36.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit to which the present invention is applied will be specifically described with reference to the drawings.

[First Embodiment] The first to fourth embodiments relate to an oscillation circuit formed on a semiconductor substrate, and are characterized in that an inductor and a capacitor are not included in the circuit.

FIG. 1 is a circuit diagram of a first embodiment of the oscillation circuit according to the present invention. 1 is an NPN type bipolar transistor (hereinafter simply referred to as a transistor).
Q1 to Q10 and bias resistors R1 to R4, r1 and r2.

Transistors Q1, Q2, Q4, Q5;
The transistors Q3, Q6, Q7, and Q8 are respectively emitter-coupled. The amplification factors of the transistors Q1 and Q5 are set by the current flowing through the bias resistor R1, and the amplification factors of the transistors Q2 and Q4 are set by the current flowing through the bias resistor R2. Similarly, transistor Q
The amplification factors of the transistors Q6 and Q8 are set by the current flowing through the bias resistor R4, and the amplification factors of the transistors Q6 and Q8 are set by the current flowing through the bias resistor R4.

The base terminal voltages of the transistors Q1 and Q8 are controlled by the collector terminal voltages of the transistors Q3 and Q7, and the base terminal voltages of the transistors Q2 and Q6 are controlled by the collector terminal voltages of the transistors Q1 and Q5. Similarly, the base terminal voltages of the transistors Q4 and Q7 are controlled by the collector terminal voltages of the transistors Q6 and Q8, and the base terminal voltages of the transistors Q3 and Q5 are controlled by the collector terminal voltages of the transistors Q2 and Q4.

The transistors Q9 and Q10 are provided to amplify the collector terminal voltages of the transistors Q3 and Q6, respectively, and the gain is determined by the resistance values of the bias resistors r1 and r2. The final oscillation outputs Out and OutB are output from the respective emitter terminals of the transistors Q9 and Q10.

One end of each of the bias resistors R1 to R4 is connected to the power supply terminal VCS, one end of each of the bias resistors r1 and r2 is connected to the power supply terminal VEE, and the collector terminals of the transistors Q9 and Q10 are connected to the power supply terminal VCC. I have.

FIG. 2 is a simplified circuit diagram of FIG. 1. The transistors Q1 to Q4 and the bias resistors R1 to R4 of FIG.
3 and r1 show an example in which an oscillation circuit is configured. The connection relationship between these transistors and the bias resistors is the same as in FIG.

Before describing the operation of FIG. 1, the operation of FIG. 2 will be described first. The voltage due to noise or the like generated when a voltage is applied to the power supply terminals VCC, VCS, VEE
When the voltage is input to the base terminal of the transistor Q1, the voltage is amplified and output from the collector terminal of the transistor Q1.

The voltage output from the collector terminal of transistor Q1 is input to the base terminal of transistor Q2 and amplified, and the amplified voltage is output from the collector terminal. The voltage output from the collector terminal of the transistor Q2 is input to the base terminal of the transistor Q3 and further amplified, and the amplified voltage is output from the collector terminal.

The voltage output from the collector terminal of transistor Q3 is input to the base terminal of transistor Q9 and also to the base terminal of transistor Q1 via feedback path P1. The direction in which the base terminal voltage of the transistor Q1 changes is opposite to the direction in which the collector terminal voltage of the transistor Q3 changes. When the base terminal voltage of the transistor Q1 increases, feedback control is performed so that the voltage decreases. Then, when the base terminal voltage of the transistor Q1 decreases, the feedback control is performed so that the voltage increases.

By such control, the transistor Q3
An oscillation signal of a predetermined frequency is output from the collector terminal of the oscilloscope. This oscillation signal is amplified by the transistor Q9, and a final oscillation output OutB is obtained from its emitter terminal.

In the oscillation circuit shown in FIG.
The oscillation frequency can be made variable by adjusting the current flowing through R3. In order to adjust the current flowing through the bias resistors R1 to R3, for example, a bias control circuit 10 as shown in FIG. 2 may be provided to variably control the voltage VCS.

On the other hand, the oscillation circuit of FIG. 1 is characterized in that the number of transistors is increased in order to perform a more stable oscillation operation. Transistors Q1-Q3, Q9 in FIG.
The operation of the bias resistors R1 to R3 and r1 is the same as that of FIG.
The operation of the oscillation circuit of FIG. 1 will be described focusing on the operation of 8, Q10 and bias resistors R4 and r2.

When the base terminal voltage of the transistor Q1 in FIG. 1 rises due to noise or the like, the base terminal voltage of the transistor Q8 also rises. Thereby, the transistor Q8
And the base terminal voltages of the transistors Q4 and Q7 decrease. Accordingly, transistor Q4
And the base terminal voltage of the transistor Q3 increases, and subsequently, the collector terminal voltage of the transistor Q3 and the base terminal voltage of the transistor Q1 decrease.

As described above, when the base terminal voltage of the transistor Q1 increases, the feedback control is performed so that the voltage decreases.

On the other hand, when the base terminal voltage of transistor Q1 decreases, the base terminal voltage of transistor Q8 also decreases, and accordingly, the collector terminal voltage of transistor Q8 and the base terminal voltages of transistors Q4 and Q7 increase. . Subsequently, the collector terminal voltage of the transistor Q4 and the base terminal voltage of the transistor Q3 decrease, and subsequently, the collector terminal voltage of the transistor Q3 and the base terminal voltage of the transistor Q1 increase.

As described above, when the base terminal voltage of the transistor Q1 decreases, feedback control is performed so that the voltage increases, and as a result, the transistors Q3 and Q3
An oscillation output of a predetermined frequency is obtained from the collector terminal 6.

In the oscillation circuit of FIG. 1, the oscillation frequency can be varied by changing the voltage VCS applied to one ends of the bias resistors R1 to R4. For example, FIG. 3 shows that the voltage VCS is 1 V, 1.2 V, 1.4 V, 1.6 V,
FIG. 9 is an oscillation output waveform diagram showing a result of an experiment performed while changing the voltage to 1.8 V and 2 V. As shown in the figure, the oscillation circuit of FIG. 1 stably oscillates at different frequencies when the voltage VCS is changed between 1 and 2V.

FIG. 4 is a diagram showing a frequency spectrum of the oscillation circuit of FIG. 1 obtained by an experiment. As in FIG. 3, each frequency spectrum when the voltage VCS is changed between 1 and 2 V is shown. Is illustrated. FIG. 3 illustrates a temporal change of the peak point of the frequency component illustrated in FIG. FIG. 5 is a diagram showing how the peak point of the frequency component changes according to the voltage VCS. These FIGS.
Power supply voltage VCC is 2.0V, ground voltage VEE is 0V, bias resistors R1 to R4 are 300Ω, and bias resistors r1 and r2 are 3k.
Ω and the transistor emitter area was 0.2 μm ² .

In the experiments shown in FIGS. 3 to 5, when the voltage VCS is changed, the oscillation frequency changes accordingly.
Is changed from 1 to 2 V, the peak of the oscillation frequency is
It changed from 1.53GHz to 4.37GHz. Also, as the voltage VCS increases, the oscillation frequency tends to increase.

As described above, in the oscillation circuit of the first embodiment, the plurality of transistors Q1 to Q10 are cascaded, and the oscillation operation is performed by adjusting the amplification factor of each transistor and performing feedback control. Since the oscillation circuit can be configured without using passive elements such as inductors and capacitors as in the related art, the entire oscillation circuit can be easily integrated. Further, the oscillation frequency can be varied over a wide range by changing the voltage applied to the bias resistors R1 to R4, and a voltage-controlled oscillation circuit having a simple circuit configuration can be obtained.

Further, in the oscillation circuit of the present embodiment, since only one transistor is connected between the power supply voltage VCC and the ground voltage VEE, the voltage levels of the power supply voltages VCC and VCS can be set low, and the power consumption can be reduced. Reduction can be achieved.

FIG. 6 is a schematic block diagram of a PLL circuit using the oscillation circuit of FIG. 1 as a voltage-controlled oscillation circuit.
The PLL circuit in FIG. 6 includes a phase comparator 11, a low-pass filter 12, a voltage-controlled oscillator 13 having the same circuit configuration as in FIG. 1, and a frequency divider 14. Voltage controlled oscillator 1
The oscillation output output from 3 is input to the phase comparator 11 after being frequency-divided by the frequency divider 14 at a predetermined frequency division ratio. The phase comparator 11 compares the phase of the output of the frequency divider 14 with the reference oscillation signal input from the outside, and outputs a signal corresponding to the amount of phase shift. This signal is supplied to the low-pass filter 12
Is input to the voltage-controlled oscillation circuit 13 via the. The voltage-controlled oscillation circuit 13 oscillates at the current frequency when the phase shift is not detected by the phase comparator 11, and oscillates at a frequency and phase that eliminates the phase shift when the phase shift is detected. .

As described above, the oscillation circuit of the first embodiment can also be used as a voltage-controlled oscillation circuit for a PLL circuit, and by using the oscillation circuit of this embodiment, the circuit configuration of the entire PLL circuit is simplified. And integration can be easily performed.

[Second Embodiment] In the second embodiment, an oscillation circuit is constituted by using MOS transistors instead of bipolar transistors.

FIG. 7 is a circuit diagram of a second embodiment of the oscillation circuit according to the present invention. The oscillator circuit of FIG. 7 has the same circuit configuration as that of FIG. 1 except that the bipolar transistors Q1 to Q10 shown in FIG. 1 are changed to MOS transistors (MOSFETs) M1 to M10.

The operation principle of the oscillation circuit of FIG. 7 is basically the same as that of FIG. 1, and the oscillation operation is performed by controlling the gate terminal voltages of the MOS transistors M1 to M8 in a feedback manner. 1 in that the oscillation frequency can be variably controlled by changing the voltage VCS at one end of the bias resistors R1 to R4.

FIG. 8 is a frequency spectrum waveform diagram of the oscillation circuit of FIG. 7 obtained by an experiment.
Each frequency spectrum when the voltage is changed to 1.2 V, 1.4 V, 1.6 V, 1.8 V, and 2 V is shown. FIG. 8 shows the gate length Lg of each of the MOS transistors M1 to M10 shown in FIG.
Is 0.36 μm and the gate width Wg is 100 μm.

As shown in the figure, the oscillation circuit shown in FIG. 7 oscillates stably at a frequency corresponding to the voltage VCS. Note that there are a plurality of peak points for each of the voltages VCS at the same level, because the oscillation output contains harmonic components.

As described above, when the oscillation circuit is configured using the MOS transistors, there is a problem that the amount of the harmonic component included in the oscillation output slightly increases as compared with the case where the oscillation circuit is configured using the bipolar transistors. However, the oscillation operation is performed normally.

In the case of a bipolar transistor, the voltage between the base and the emitter cannot be made lower than about 0.7 V. However, in the case of a MOS transistor, there is no such limitation. 7 can set the voltages VCC and VCS of FIG. 7 to a lower voltage, and can further reduce the power consumption.

[Third Embodiment] In a third embodiment, the circuit configuration of the oscillation circuit is a bipolar transistor and a MOS transistor.
This is a BiCMOS configuration combining transistors.

FIG. 9 is a circuit diagram of a third embodiment of the oscillation circuit according to the present invention. In the oscillation circuit of FIG. 9, the bias resistors R1 to R4 shown in FIG. 1 are configured by diode-connected transistor constant current sources. Specifically, a P-type MOS transistor (hereinafter, referred to as a PMOS transistor) )
R1 'to R4' substitute for a bias resistor. Other configurations are the same as those of the oscillation circuit of FIG.

FIG. 10 is a frequency spectrum waveform diagram of the oscillation circuit of FIG. 9 obtained by an experiment.
V, 1.2 V, 1.4 V, 1.6 V, 1.8 V, and 2 V show respective frequency spectra when changed. Note that FIG.
Is the gate length Lg of the PMOS transistors R1 'to R4'.
The results of an experiment performed with 0.36 μm and a gate width Wg of 100 μm are shown.

As shown in the figure, the oscillation circuit of FIG. 9 also oscillates stably at a frequency corresponding to the voltage VCS. However,
As in the second embodiment, the amount of the harmonic component included in the oscillation output is larger than in the first embodiment. The oscillation circuit of FIG. 9 uses a bipolar transistor.
Since the current driving force is essentially higher than that of the MOS transistor, the time required to obtain a desired logic amplitude is shorter than in the second embodiment. Therefore, the oscillation frequency can be increased.

[Fourth Embodiment] In the fourth embodiment, a bias resistor is provided on the emitter side of each transistor constituting an oscillation circuit.

FIG. 11 is a circuit diagram of a fourth embodiment of the oscillation circuit according to the present invention. In the oscillation circuit of FIG. 11, a bias resistor R5 is connected to each of the emitter terminals of the transistors Q1, Q2, Q4, and Q5 shown in FIG.
A bias resistor R6 is connected to each of the emitter terminals of Q6 to Q8, and one end of each of the bias resistors R5, R6, r1, and r2 is set to the ground voltage VEE.

The bias resistor R5 is connected to the transistors Q1,
The current flowing through each of the emitter terminals of Q2, Q4 and Q5 is controlled, and the bias resistor R6 is connected to the transistors Q3, Q6 to Q5.
8 controls the current flowing through each emitter terminal.

The oscillating circuit of FIG. 11 performs an oscillating operation according to the same principle as that of FIG. 1, and newly added bias resistors R5 and R6.
Oscillating frequency is variably controlled by controlling the bias current flowing through. For example, by providing a bias control circuit 10 'as shown in FIG. 11 and changing the voltage level of the ground voltage VEE, the bias resistors R5, R6, r1, r2
The current flowing through the oscillator changes, and the oscillation frequency changes.

When the oscillation frequency of the oscillation circuit shown in FIG. 11 is variably controlled, not only the ground voltage VEE but also the power supply voltage VCS may be changed at the same time.

In the above-described first to third embodiments, the oscillation frequency is variably controlled by controlling the voltage level of the power supply voltage CS.
Although there is a problem that the variable range of the voltage is limited by the CC, the voltage level of the ground voltage VEE is variable in the present embodiment, so that the variable range of the voltage is wide,
The oscillation frequency can be changed in a wide range.

As in the case of FIG. 11, a bias resistor may be connected to the source terminal of each of the MOS transistors M1 to M8 of FIG.
A bias resistor may be connected to the emitter terminal of Q8.

The bias resistors R1 to R8 shown in FIG. 11 and the like may be constituted by discrete resistance elements, but may be constituted by using active elements such as MOSFETs.

In FIGS. 1, 2, 9, and 11, an example in which an oscillation circuit is formed using NPN transistors has been described.
As shown in FIG. 2, an oscillation circuit may be configured using PNP transistors. Alternatively, an oscillation circuit may be formed using P-type MOS transistors, or an oscillation circuit may be formed using CMOS transistors. Further, instead of the PMOS transistors R1 'to R4' shown in FIG. 9, a bias resistor may be constituted by an NMOS transistor.

[Fifth Embodiment] The fifth to fifth embodiments described below.
The seventh embodiment relates to a frequency dividing circuit formed on a semiconductor substrate.

FIG. 13 is a circuit diagram of a fifth embodiment of the semiconductor integrated circuit according to the present invention, and shows a configuration of a frequency dividing circuit for dividing a clock signal by two.

The circuit of FIG. 13 includes a transconductance unit 21 for outputting a complementary signal corresponding to a clock signal IN input from the outside, and a frequency dividing unit 22 for dividing the output of the transconductance unit 21 by two.

The transconductance unit 21 outputs a differential amplifier 23 that outputs complementary signals I1 and I2 according to the voltage difference between the clock signal IN and its inverted signal INB, and an impedance that converts the output impedance of the differential amplifier 23. It has a converter 24, a constant current source 25 connected to the differential amplifier 23, and an input controller 26 for controlling a base voltage of the differential amplifier 23.

The differential amplifier 23 includes a transistor Q21 whose base terminal receives a clock signal IN, a transistor Q22 whose base terminal receives an inverted signal INB of the clock signal IN, a transistor Q21 and a power supply voltage terminal Vcc.
And a resistor R22 connected between the transistor Q22 and the power supply voltage terminal Vcc.

The impedance converter 24 includes transistors Q23 and Q24 connected in emitter follower, a transistor Q26 and a resistor R24 for controlling a current flowing between the collector and the emitter of the transistor Q23, and a transistor Q24.
A transistor Q27 and a resistor R25 for controlling the current flowing between the collector and the emitter of the transistor Q27. Transistor Q2
The base terminal of the transistor 3 is connected to the collector terminal of the transistor Q22, and the power supply voltage Vcc is applied to the collector terminal of the transistor Q23. The base terminal of the transistor Q24 is connected to the collector terminal of the transistor Q21, and the power supply voltage Vcc is applied to the collector terminal of the transistor Q24.

The collector terminal of the transistor Q26 is connected to the emitter terminal of the transistor Q23, and the emitter terminal of the transistor Q26 is connected to one end of the resistor R24.
The other end of 24 is grounded. The collector terminal of the transistor Q27 is connected to the emitter terminal of the transistor Q24, the emitter terminal of the transistor Q27 is connected to one end of the resistor R25, and the other end of the resistor R25 is grounded.

The constant current source 25 comprises a transistor Q25 and a resistor R23. The collector terminal of the transistor Q25 is connected to the emitter terminals of the transistors Q21 and Q22.
The emitter terminal of Q25 is connected to one end of a resistor R23, and the other end of the resistor R23 is grounded.

The input control section 26 includes transistors Q28 and Q28.
29 and a resistor R26. Transistor Q28 functions as a constant voltage source that stably supplies a forward voltage of a pn junction between its base and emitter. The current flowing through transistor Q28 is controlled by transistor Q29 and resistor R26.
A resistor R27 is connected between the emitter terminal of the transistor Q28 and the base terminal of the transistor Q21, and a resistor R28 is connected between the emitter terminal of the transistor Q28 and the base terminal of the transistor Q22.

On the other hand, frequency dividing section 22 is the same as FIG. 20 in that it is constituted by a T-type flip-flop, but is different from the T-type flip-flop of FIG. 20 in that it is connected in series between power supply voltage Vcc and the ground terminal. The number of transistors to be used is limited to two or less.

The transistors Q30 to Q39 and the resistor R29 shown in FIG.
R34 are the main part of the T-type flip-flop, and the transistor Q34 and the resistor R31 are composed of transistors Q30, Q31, Q37,
The current flowing through Q38 is controlled, and transistor Q39 and resistor R34
Controls the current flowing through the transistors Q32, Q33, Q35, Q36. Also, transistors Q40 to Q43 and resistors R35 and R36
Is provided to lower the output impedance of the frequency divider 22.

Hereinafter, the configuration of the frequency dividing section 22 will be described in detail. Collector terminal of transistor Q30, transistor Q3
3, the base terminal of Q35 and one end of resistor R29 are connected to each other, and power supply voltage Vcc is applied to the other end of resistor R29.
In addition, the collector terminal of the transistor Q31 and the transistor Q
The base terminals of the resistors 32 and Q36 and one end of the resistor R30 are connected to each other, and the other end of the resistor R30 is applied with the power supply voltage Vcc.

The collector terminal of the transistor Q35,
Base terminals of transistors Q31, Q38, Q40 and resistor R32
Are connected to each other, and the power supply voltage Vcc is applied to the other end of the resistor R32. The collector terminal of the transistor Q36, the base terminals of the transistors Q30, Q37 and Q41, and one end of the resistor R33 are connected to each other, and the other end of the resistor R33 is applied with the power supply voltage Vcc.

The transistors Q23, Q30, Q31, Q3
The emitter terminals of Q7 and Q38 and the collector terminal of transistor Q34 are connected to each other, and transistors Q24, Q32, Q33,
The emitter terminals of 35 and Q36 and the collector terminal of transistor Q39 are connected to each other. The emitter terminal of the transistor Q34 is grounded via the resistor R31,
The emitter terminal of Q39 is grounded via a resistor R34.

The transistors Q40 and Q41 are connected in an emitter-follower configuration to convert the output impedance. The bias current flowing between the collector and the emitter of the transistor Q40 is controlled by the transistor Q42 and the resistor R35, and the current flowing between the collector and the emitter of the transistor Q41 is controlled by the transistor Q43 and the resistor R36. Further, transistors Q25 to Q27, Q29, Q34, Q
The base terminals of 39, Q42, and Q43 are connected to each other and set to a predetermined voltage value (for example, 1.0 V).

FIG. 14 is an operation timing chart of the frequency dividing circuit of FIG. 13. The operation of the frequency dividing circuit of FIG. 13 will be described with reference to FIG. The differential amplifier 23 supplies complementary signals I1, I2 corresponding to the voltage difference between the clock signal IN and its inverted signal INB.
2 is output. The complementary signals I1 and I2 are input to the base terminals of the transistors Q24 and Q23, respectively, are subjected to impedance conversion, and the signals EF1 and EF2 are output from the emitter terminals of the transistors Q23 and Q24, respectively. These signals EF1 and EF2 are signals CLK and CLK of FIG.
B is a signal corresponding to B.

The frequency divider 22 inverts the output logic each time the signal EF1 goes high. For example, FIG.
Shows an example in which the transistor Q40 is turned on during the period from time T1 to T2, and the output OUT of the frequency divider 22 becomes high level. At this time, since the base voltage of the transistor Q40 becomes high level and the signal EF1 is at low level, the transistor Q38 turns on, the collector voltage of the transistor Q38 and the base voltage of the transistor Q41 become low level, and the transistor Q41 Turns off and output O
UTB goes low.

At times T1 and T2, the transistors
The base voltage of Q31 becomes high level, and the transistor Q31
Turns on, and the base voltages of the transistors Q32 and Q36 become low level. Further, the transistor Q30 is turned off, and the base voltages of the transistors Q33 and Q35 go to a high level.

Next, during a period from time T2 to time T3 in FIG. 14, the signal EF1 is at a high level and the signal EF2 is at a low level. Therefore, the transistors Q30 and Q31 are both turned off. Immediately before the time T2, the base voltages of the transistors Q32 and Q36 are at the low level and the base voltages of the transistors Q33 and Q35 are at the high level, so that the base voltages of these transistors maintain their states. Therefore, transistors Q33 and Q35 are both turned on and transistor Q3
8. The base voltage of Q40 drops, transistor Q40 turns off and output OUT goes low. Also, the transistor Q
Since both 32 and Q36 are off, transistors Q37 and Q41
Rises, the transistor Q41 turns on, and the output OUTB goes high.

Next, during a period between times T3 and T4 in FIG. 14, the signal EF1 is at a low level and the signal EF2 is at a high level. During this period, since the transistors Q35 and Q36 are off, the states of the transistors Q40 and Q41 do not change.
The logic of the outputs Out and OutB does not change. Similarly, at time T4
Thereafter, the logic of the outputs Out and OutB changes at the rising edge of the clock signal INB.

Next, the power supply voltage level of the frequency dividing circuit of FIG. 13 will be examined. As described above, in order to operate the frequency dividing circuit at high speed, it is desirable to operate the transistor acting as an active element in the circuit of FIG. 13 in an active state.
For this purpose, the collector-emitter voltage VCE of each transistor needs to be about 0.6 V or more. FIG.
In the circuit of No. 3, since two transistors are connected in series between the power supply voltage Vcc and the ground terminal, a voltage of 0.6 × 2 = 1.2 V is required at a minimum. Taking into account the load resistance such as the resistor R29 and the voltage drop in the bias circuit 26, a stable operation is guaranteed by setting the power supply voltage Vcc to about 1.9V.

FIGS. 15 and 16 show the resistances R21 and R22 of FIG.
Is 800Ω, the resistance of resistors R27 and R28 is 1 kΩ,
The resistance values of the resistors R23 to R26, R31, R34, R35 and R36 are set to 10
0Ω, the resistance values of the resistors R29, R30, R32 and R33 are 300Ω, the power supply voltage Vcc is 1.9V, and the input terminals IN and IN of the circuit of FIG.
A 10 MHz sine wave signal is input to INB and output terminals OUT,
FIG. 9 is a waveform chart showing a result of an experiment performed by connecting a spectrum analyzer to OUTB.

FIG. 15 shows input / output voltage waveforms of the frequency dividing circuit of FIG. 13, where the horizontal axis represents time and the vertical axis represents voltage amplitude.
In FIG. 15, a curve A represents an input voltage waveform, a curve B represents a voltage waveform of the output OUT, and a curve C represents a voltage waveform of the output OUTB. On the other hand, FIG. 16 shows the frequency spectrum of the frequency dividing circuit of FIG. 13, where the horizontal axis represents the frequency and the vertical axis represents the voltage amplitude.

As can be seen from FIG. 15, the frequency divider circuit shown in FIG. 13 outputs signals OUT and OUT which are almost square waves having a period twice as long as the input signal IN.
Output B. From FIG. 16, the frequency of the output signals OUT and OUTB is exactly 5 MHz. In addition, in FIG.
, A peak point is found, which is a harmonic component.

As described above, the frequency dividing circuit according to the present embodiment includes a transconductance unit 2 for driving a clock signal.
1 is newly provided, and the number of transistors connected in series between the power supply voltage Vcc in the frequency dividing circuit and the ground terminal is limited to two. Therefore, the power supply voltage Vcc is lower than that of the conventional frequency dividing circuit shown in FIG. , A stable divided output can be obtained, as shown in FIG.

[Sixth Embodiment] In the sixth embodiment, the MO
A frequency dividing circuit is configured using SFETs. FIG. 17 is a circuit diagram of a sixth embodiment of the semiconductor integrated circuit according to the present invention, and shows a configuration of a frequency dividing circuit. The frequency divider of FIG. 17 has the same circuit configuration as that of FIG. 13 except that a MOSFET is used instead of a bipolar transistor.

In the frequency dividing circuit shown in FIG. 17, the transistor functioning as an active element is an N-type MOSFET and the load resistance is a P-type MOSFET.
It is composed of MOSFET. The frequency dividing circuit of FIG. 17 also limits the number of MOSFETs connected in series between the power supply voltage Vcc and the ground terminal to two or less, so that the voltage level of the power supply voltage Vcc can be lowered. Further, by controlling the threshold voltage of each MOSFET, the power supply voltage Vcc can be set to a lower voltage level.

[Seventh Embodiment] In the seventh embodiment, the MO
A frequency dividing circuit is configured using both SFETs and bipolar transistors. FIG. 18 is a circuit diagram of a seventh embodiment of the semiconductor integrated circuit according to the present invention, and shows a configuration of a frequency dividing circuit. In the frequency dividing circuit of FIG. 18, the transistor functioning as an active element is constituted by an NPN-type bipolar transistor, and the load resistance is constituted by a P-type MOSFET.

Bipolar transistors are generally MOSFETs
It has the characteristics of higher operating speed, higher current driving capability, and higher power consumption. For this reason, as shown in FIG. 18, when a bipolar transistor is used only in a portion of the frequency divider circuit requiring high-speed operation and MOSFETs are used in other portions, power consumption can be reduced and operation speed can be improved. .

The specific circuit configuration of the frequency dividing circuit is not limited to those shown in FIGS. For example, the circuit may be configured by a CMOS process. Also, MOSF
Even when the ET and the bipolar transistor are mixed to form a BiCMOS configuration, the allocation of the MOSFETs and the bipolar transistors is not limited to that shown in FIG. Further, the frequency dividing circuit may be configured using a flip-flop other than the T-type flip-flop, for example, a D-type flip-flop.

The oscillation circuits described in the first to fourth embodiments and the frequency divider circuits described in the fifth to seventh embodiments may be formed on the same semiconductor substrate. Or,
The PLL circuit shown in FIG. 6 may be formed on a semiconductor substrate using the oscillation circuit described in the first to fourth embodiments and the frequency divider circuit described in the fifth to seventh embodiments. Good.

In the fifth to seventh embodiments, one end of the resistor R23 and the like is grounded. However, a predetermined voltage may be applied to one end of the resistor R23 and the like.

[0121]

As described above in detail, according to the present invention, an oscillation circuit is formed by combining a plurality of transistors and a bias circuit without using passive elements such as capacitors and coils which are difficult to integrate. In addition, the entire oscillation circuit can be easily integrated on a semiconductor substrate. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced. Also, the chip size can be reduced.

Further, by controlling the current flowing through the bias circuit, the oscillation frequency can be changed, and it can be used as a voltage-controlled oscillation circuit widely used in PLL circuits and the like.

Further, according to the present invention, a frequency dividing circuit is constituted by using the frequency dividing section and the complementary clock output section. In the frequency dividing section and the complementary clock output section, between the first and second voltage terminals,
Since three or more transistors functioning as active elements are not connected in series, the voltage between the first and second voltage terminals can be reduced, and the power consumption of the frequency divider can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of an oscillation circuit according to the present invention.

FIG. 2 is a circuit diagram obtained by simplifying FIG. 1;

FIG. 3 is an oscillation output waveform diagram in a state where a voltage VCS is changed.

FIG. 4 is a diagram showing a frequency spectrum of the oscillation circuit of FIG. 1 obtained by an experiment.

FIG. 5 is a diagram showing how a peak point of a frequency component changes according to a voltage VCS.

FIG. 6 is a schematic block diagram of a PLL circuit using the oscillation circuit of FIG. 1 as a voltage-controlled oscillation circuit.

FIG. 7 is a circuit diagram of an oscillator circuit according to a second embodiment of the present invention.

8 is a diagram showing a frequency spectrum of the oscillation circuit of FIG. 7 obtained by an experiment.

FIG. 9 is a circuit diagram of an oscillation circuit according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a frequency spectrum of the oscillation circuit of FIG. 9 obtained by an experiment.

FIG. 11 is a circuit diagram of an oscillation circuit according to a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram of an oscillator circuit including PNP transistors.

FIG. 13 is a circuit diagram of a frequency dividing circuit according to a fifth embodiment of the semiconductor integrated circuit.

FIG. 14 is an operation timing chart of the frequency dividing circuit of FIG. 13;

FIG. 15 is a diagram showing input / output voltage waveforms of the frequency dividing circuit of FIG. 13;

FIG. 16 is a diagram showing a frequency spectrum of the frequency dividing circuit of FIG. 13;

FIG. 17 is a circuit diagram of a frequency dividing circuit according to a sixth embodiment of the semiconductor integrated circuit.

FIG. 18 is a circuit diagram of a frequency dividing circuit according to a seventh embodiment of the semiconductor integrated circuit.

FIG. 19 is a circuit diagram of a conventional Colpitts oscillation circuit.

FIG. 20 is a circuit diagram of a conventional T-type flip-flop.

[Explanation of symbols]

 10, 10 'bias control circuit 21, 21', 21 "transconductance section 22, 22 ', 22" frequency dividing section Q1 to Q10, Q21 to Q43 bipolar transistor M1 to M10, M21 to M47 MOS transistor

Claims (20)

[Claims] 1. An emitter-coupled or source-coupled first device.
And a second transistor; a third transistor whose base terminal voltage or gate terminal voltage changes according to a collector terminal voltage or a drain terminal voltage of the second transistor; and setting an amplification factor of the first transistor. A first bias circuit that sets an amplification factor of the second transistor; and a third bias circuit that sets an amplification factor of the third transistor. The base terminal voltage or the source terminal voltage of the third transistor is controlled according to the collector terminal voltage or the drain terminal voltage of the third transistor, and the base terminal voltage or the source terminal voltage of the second transistor is the first terminal voltage. The third transistor is controlled according to a collector terminal voltage or a drain terminal voltage of the transistor; A semiconductor integrated circuit which outputs an oscillation signal from a collector terminal or a drain terminal of a star. Each of the first to third bias circuits includes an impedance element having one end connected to the other; and adjusting the voltage at one end of the impedance element connected to the other, thereby controlling the oscillation. 2. The semiconductor integrated circuit according to claim 1, further comprising a first bias control circuit that variably controls a signal oscillation frequency. A first bias circuit for setting an amplification factor of the first and fifth transistors; and a first bias circuit for setting an amplification factor of the second and fourth transistors. A second bias circuit, a third bias circuit for setting the amplification factors of the third and seventh transistors, and a fourth bias circuit for setting the amplification factors of the sixth and eighth transistors. The emitter terminals or source terminals of the first, second, fourth and fifth transistors are connected to each other, and the emitter terminals or source terminals of the third, sixth, seventh and eighth transistors are connected to each other. The base terminal voltage or the source terminal voltage of the first and eighth transistors is the collector terminal voltage or the drain terminal voltage of the third and seventh transistors. The base terminal voltage or the source terminal voltage of the second and sixth transistors is controlled according to the collector terminal voltage or the drain terminal voltage of the first and fifth transistors; And the base terminal voltage or the source terminal voltage of the seventh transistor is controlled according to the collector terminal voltage or the drain terminal voltage of the sixth and eighth transistors, and the base terminal voltage or the base terminal voltage of the third and fifth transistors The source terminal voltage is controlled according to the collector terminal voltage or the drain terminal voltage of the second and fourth transistors, and outputs an oscillation signal from the collector terminal or the drain terminal of the third and sixth transistors, respectively. Characteristic semiconductor integrated circuit. 4. The oscillating circuit according to claim 1, wherein each of the first to fourth bias circuits includes an impedance element having one end connected to one another, and adjusting the voltage at one end of the impedance element connected to one another. 4. The semiconductor integrated circuit according to claim 3, further comprising a first bias control circuit that variably controls a signal oscillation frequency. 5. A fifth transistor for controlling a current flowing through an emitter terminal or a source terminal of said first and second transistors.
The semiconductor integrated circuit according to claim 1, further comprising: a bias circuit configured to control a current flowing through an emitter terminal or a source terminal of the third transistor. 6. A fifth bias circuit for controlling a current flowing through said first, second, fourth and fifth emitter terminals or source terminals, and said third, sixth, seventh and eighth emitters. 5. The semiconductor integrated circuit according to claim 3, further comprising: a sixth bias circuit for controlling a current flowing through the terminal or the source terminal. 7. The fifth and sixth bias circuits each include an impedance element having one end connected to one another, and adjusting the voltage at one end of the impedance element connected to one another to adjust the oscillation. 7. The semiconductor integrated circuit according to claim 6, further comprising a second bias control circuit that variably controls a signal oscillation frequency. 8. A ninth transistor that amplifies and outputs a collector terminal voltage or a drain terminal voltage of the third transistor, and outputs an amplified oscillation signal from an output side of the ninth transistor. 6. The semiconductor integrated circuit according to claim 1, wherein: 9. A ninth transistor for amplifying and outputting a collector terminal voltage or a drain terminal voltage of the third transistor, and a ninth transistor for amplifying and outputting a collector terminal voltage or a drain terminal voltage of the sixth transistor. 10. The semiconductor according to claim 3, further comprising: ten transistors; and outputting an amplified oscillation signal from an output side of the ninth and tenth transistors. Integrated circuit. 10. The semiconductor integrated circuit according to claim 9, wherein at least a part of said first to tenth transistors is a bipolar transistor. 11. The semiconductor integrated circuit according to claim 9, wherein at least a part of said first to tenth transistors is a MOS transistor. 12. The apparatus according to claim 3, wherein each of the first to fourth bias circuits includes a diode-connected MOS transistor. A semiconductor integrated circuit as described in the above. 13. A semiconductor integrated circuit having a frequency divider for outputting a frequency-divided signal obtained by dividing an externally input clock signal by an integral multiple, wherein a frequency difference between the clock signal and an inverted signal thereof is determined. A complementary clock output unit that outputs a complementary signal, the frequency divider outputs the frequency-divided signal based on the complementary signal, and the frequency divider and the complementary clock output unit include a power supply voltage, A first and a second voltage are supplied, and the frequency divider and the complementary clock output are respectively
A semiconductor integrated circuit comprising a plurality of transistors functioning as active elements, wherein the number of said transistors connected in series between said first and second voltage terminals is two or less. 14. The frequency dividing section and the complementary clock output section each include a transistor connected between the first and second voltage terminals and functioning as an active element, and a transistor between the transistor and the first voltage terminal. A plurality of current paths each including a connected impedance element and a bias circuit connected between the transistor and the second voltage terminal and controlling a current flowing through the transistor;
14. The current path, wherein two or less transistors functioning as active elements are connected in series.
3. The semiconductor integrated circuit according to claim 1. 15. The device according to claim 15, wherein said bias circuit in said frequency divider and said complementary clock output unit controls a current flowing through said transistor so that the transistor to be controlled operates in an active region. Item 15. A semiconductor integrated circuit according to item 14. 16. A differential amplifier for outputting a signal corresponding to a voltage difference between the clock signal and its inverted signal, a constant current source for controlling a current flowing in the differential amplifier, A first impedance conversion circuit that performs impedance conversion on the output of the differential amplifier and outputs the complementary signal, and wherein the differential amplifier and the constant current source 16. The first impedance conversion circuit is connected in series between two voltage terminals, and the first impedance conversion circuit is connected between the first and second voltage terminals. Semiconductor integrated circuit. 17. The frequency divider has a T-type flip-flop for inverting output logic at one of a rising edge and a falling edge of a signal output from the complementary clock output unit. 17. The flip-flop according to claim 13, wherein a plurality of transistors functioning as active elements are provided, and the number of said transistors connected in series between said first and second voltage terminals is two or less. A semiconductor integrated circuit according to any one of the above. 18. The frequency dividing unit has a second impedance conversion circuit that performs impedance conversion on the T-type flip-flop and outputs the frequency-divided signal. 18. The semiconductor integrated circuit according to claim 17, wherein the semiconductor integrated circuit is connected between the first and second voltage terminals. 19. A semiconductor integrated circuit according to claim 1 and a semiconductor integrated circuit according to claim 13 formed on the same semiconductor substrate. Semiconductor integrated circuit. 20. An apparatus according to claim 19, wherein an oscillation signal output from the semiconductor integrated circuit according to any one of claims 1 to 12 is supplied to said complementary clock output section as said clock signal. Semiconductor integrated circuit.