JPH1187661A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve isolation capacity in a memory cell region by forming a second isolation diffused layer only directly under an inter-element isolation oxide film in the cell region, thereby preventing a decrease in a connecting withstand voltage in a peripheral circuit region. SOLUTION: LOCOS films 18a, 18b, 18c are formed on a substrate 11 by an inter-element isolation (LOCOS) method. An N-type well region 17 and an N<+> type isolation 20, and further a P-type well region 16 and P<+> type isolation 19 are formed by ion implanting. After a gate oxide film 22a and a polysilicon film are deposited, a photoresist film is formed, and patterned. A floating gate 23 is formed at a memory cell region 12 by etching with the photoresist film used as a mask. Further, with the photoresist film used as a mask, ion implanting is executed, and a second P<+> type isolation 21 is locally formed directly under LOCOS oxide films 18a, 18b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device, and more particularly to a device isolation structure of a nonvolatile memory.

[0002]

2. Description of the Related Art FIG. 15 is a sectional view showing a separation structure in a conventional semiconductor device for a DINOR type EEPROM. In the figure, reference numeral 1 denotes a semiconductor substrate made of a P-type silicon single crystal or the like (hereinafter, referred to as a substrate 1);
The memory cell region 3 of the ROM, the peripheral circuit region 3 of the EEPROM, and the reference numerals 4 and 5 are the N-type transistor formation region and the P-type transistor formation region in the peripheral circuit region 3. 6 is a P-type well region formed on the substrate 1, 7 is an N-type well region, 8 is a LOCOS oxide film for isolating elements,
Reference numeral 9 denotes a P ⁺ -type isolation diffusion layer formed in the P-type well region 6 for device isolation (hereinafter referred to as P ⁺ -isolation), and reference numeral 10 denotes a device isolation formed in the N-type well region 7. N ⁺ type isolation diffusion layer (hereinafter, referred to as N ⁺ isolation).

As shown in FIG. 1, a LOCOS oxide film 8 is formed on a substrate 1, and isolations 9 and 10 are buried under the LOCOS oxide film 8 to separate elements. In the conventional semiconductor device as described above, first, the LOCOS method is applied to the substrate 1 to form the LOCOS oxide film 8 in the memory cell region 2 and the peripheral circuit region 3 at the same time. 9 and 10 are formed. The formation of the isolations 9 and 10 is to form the P ⁺ isolation 9 in the P-type well region 6 and the N ⁺ isolation 10 in the N-type well region 7, respectively.

[0004]

As described above, in the conventional semiconductor device, the LOCOS oxide film 8 and the isolation layers 9, 10 for separating the elements are divided into the memory cell region 2 and the peripheral circuit region 3. And formed at the same time. In the memory cell area 2, since demands for miniaturization and high integration are high and the size of the memory cell itself is small, the LOCOS
The width of oxide film 8 also needs to be reduced. Therefore, the separation width of the LOCOS oxide film 8 in the memory cell region 2 is smaller than that in the peripheral circuit region 3 in which the size of the transistor itself is relatively large.

As described above, in the memory cell area 2, the LOC
Since the isolation width of the OS oxide film 8 is small, it is necessary to increase the concentration of the isolations 9 and 10 to a certain level in order to secure the isolation ability. As the concentration of the substrate 1 increases, the source / drain regions of the transistor (not shown)
Breakdown voltage between the substrate and the substrate 1 is reduced. Here, a voltage of, for example, about ± 15 V is applied to the peripheral circuit area 3, and a voltage of, for example, about ± 10 V is applied to the memory cell area 2, and the applied voltage is higher in the peripheral circuit area 3. For this reason, a high junction breakdown voltage is required in the peripheral circuit region 3. However, in the conventional semiconductor device, as described above, if the isolations 9 and 10 are formed at a high concentration in order to secure the separation capability in the memory cell region 2, The junction breakdown voltage in the peripheral circuit region 3 decreases,
There is a problem that the reliability is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the isolation capability in a fine memory cell region and the junction breakdown voltage in a peripheral circuit region. It is an object of the present invention to obtain a nonvolatile memory that can be used.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device having a memory cell region of a nonvolatile memory having a floating gate and a peripheral circuit region on a semiconductor substrate. LOCOS oxide film and an isolation diffusion layer below the LOCOS oxide film,
A second isolation diffusion layer is provided in both the memory cell region and the peripheral circuit region, and is provided only under the LOCOS oxide film in the memory cell region.

According to a second aspect of the present invention, there is provided a semiconductor device comprising:
2. The semiconductor device according to claim 1, wherein the LOCOS oxide film in the memory cell region is thinner than that in the peripheral circuit region, exceeding a film thickness difference caused by a difference in width of the LOCOS oxide film.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming a LOCOS oxide film on a semiconductor substrate; a second step of forming an isolation diffusion layer by ion implantation; A third step of depositing a polysilicon film serving as a floating gate via an oxide film and then patterning the floating gate in the memory cell region using a resist mask, and then a second step of ion implantation using the resist mask And a fourth step of forming an isolation diffusion layer.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of forming a LOCOS oxide film on a semiconductor substrate; a second step of forming an isolation diffusion layer by ion implantation; A third step of depositing a polysilicon film serving as a floating gate via an oxide film and then patterning the floating gate in a memory cell region using a resist mask, removing the resist film and using the polysilicon film as a mask Fourth forming a second isolation diffusion layer by ion implantation
And the step of

According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor device according to the third or fourth aspect, the formation of the LOCOS oxide film in the first step is performed by first setting the LOCOS oxide film in the peripheral circuit region. Then, the LOCO is again applied to the peripheral circuit area and the memory cell area.
This is performed by applying the S method.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to any one of the third to fifth aspects, wherein the patterning of the floating gate in the third step comprises the steps of: At
After the polysilicon film is left on the entire surface and a second isolation diffusion layer is formed thereafter, the polysilicon film in the peripheral circuit region is removed.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, at least a part of the peripheral circuit region is patterned when the floating gate is patterned in the third step.
The gate electrode of the MOS transistor is formed by patterning.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention for a DINOR type EEPROM. FIG. 2A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB of FIG. 1 and 2, reference numeral 11 denotes a semiconductor substrate made of a P-type silicon single crystal or the like (hereinafter, referred to as a substrate 11).
12 is an EEPROM memory cell area, 13 is an EEPROM
OM peripheral circuit area, 14 and 15 are peripheral circuit area 1
3 is an N-type transistor formation region and a P-type transistor formation region.

Further, 16 is a P-type well region formed on the substrate 11, 17 is an N-type well region, 18a, 18b, 1
Reference numeral 8c denotes a LOCOS oxide film for separating the elements,
a is a LOCOS oxide film in the memory cell region 12;
8b is a LOCOS oxide film located at a boundary between the memory cell region 12 and the peripheral circuit region 13, and 18c is a peripheral circuit region 1
3 is a LOCOS oxide film. Reference numeral 19 denotes a P ⁺ -type isolation diffusion layer formed in the P-type well region 16 for element isolation (hereinafter, referred to as P ⁺ -isolation), and reference numeral 20 denotes an N-type well region formed in the N-type well region 17. An N ⁺ -type isolation diffusion layer for element isolation (hereinafter referred to as N ⁺ isolation) 21 is a LOC of the memory cell region 12 including a boundary with the peripheral circuit region 13.
A second isolation diffusion layer (hereinafter, referred to as a second P ⁺ isolation) locally formed immediately below the OS oxide films 18a and 18b.

Reference numeral 22a denotes a gate oxide film formed in the memory cell region 12, 22b denotes a gate oxide film formed in the peripheral circuit region 13, and 23 denotes a gate oxide film on the memory cell region 12 of the substrate 11 via the gate oxide film 22a. , A floating gate made of polysilicon, 24 is an interpoly insulating film formed on the floating gate 23, and 25 is made of polysilicon formed on the floating gate 23 with the interpoly insulating film 24 interposed therebetween. A control gate; 26, a gate electrode made of polysilicon formed on the peripheral circuit region 13 of the substrate 11 via the gate oxide film 22b; 27, a silicide film formed on the control gate 25 and the gate electrode 26; Reference numeral 28a denotes a source formed in the memory cell region 12.
The drain region 28b is a source / drain region formed in the peripheral circuit region 13.

A method of manufacturing a semiconductor device having such a configuration will be described below with reference to FIGS. First, the substrate 11
LOCOS oxide films 18a, 18
b, 18c are formed. At this time, in the memory cell region 12, the LOCOS oxide film 18a is formed, for example, to have a width (design dimension) of about 0.5 μm and a thickness of about 0.7 μm, and the LOCOS oxide film 18a located at the boundary between the peripheral circuit region 13 and the memory cell region 12 is formed. The oxide films 18b and 18c are formed to have a width of about 1.0 μm and a thickness of about 1.0 μm, for example. LO
In the formation of the COS oxide films 18a, 18b and 18c, if the width is small, the film thickness is reduced accordingly when oxidized (FIG. 3).

Next, after a photoresist film 29 is formed on the entire surface, the photoresist film 29 in the P-type transistor formation region 15 in the peripheral circuit region 13 is opened, and ion implantation 30 is performed from above the substrate 11 to form an N-type well region 17. The formation of
Further, an N ⁺ isolation 20 is formed. This N ⁺
The isolation 20 is formed, for example, by implanting N-type impurity phosphorus at an implantation energy of about 800 KeV and burying it in the N-type well region 17 (FIG. 4).

Next, after removing the photoresist film 29,
Using the resist mask 31 again, ion implantation 32 is performed on the N-type transistor formation region 14 and the memory cell region 12 in the peripheral circuit region 13 from above the substrate 11 to form the P-type well region 16 and further perform the P ⁺ isolation 1
9 is formed. The formation of the P ⁺ isolation 19 is performed, for example, by implanting boron as a P-type impurity at an energy of 30;
It is implanted at about 0 KeV and buried in the P-type well region 16. In the N-type transistor formation region 14 of the peripheral circuit region 13, the source
The junction breakdown voltage between the drain region 28b and the substrate 11 is, for example, ±
The injection amount is set so that 12 V or more can be secured. By the way, isolations 19 and 20 used for element isolation are as follows.
It is sufficient if the layer is formed in the region below the LOCOS oxide films 18a, 18b and 18c.
0, 32, the LOCOS oxide films 18a, 18
There is no problem in regions other than the regions where b and 18c are formed, since they are deeply embedded in the substrate 11 (FIG. 5).

Next, after removing the photoresist film 31,
Forming a gate oxide film 22a made of a thermal oxide film on the entire surface;
A polysilicon film 23a is deposited over the entire surface. Next, a photoresist film 3 is formed on the entire surface of the polysilicon film 23a.
3 is formed and patterned. This photoresist film 3
3 is used as a mask to etch the underlying polysilicon film 23a so that the polysilicon film 23a
Is formed, and the polysilicon film 23a is left over the entire surface of the peripheral circuit region 13. Subsequently, ion implantation 34 is performed from above the substrate 11 using the photoresist film 33 as a mask, and the second P ⁺ isolation 2
Form one. This second P ⁺ isolation 21
For example, P-type impurity boron is implanted at an energy of 300K.
Implantation is performed at about eV and locally formed just below the LOCOS oxide films 18a and 18b in the memory cell region 12 including the boundary with the peripheral circuit region 13. At this time, the memory cell area 1
In step 2, the implantation amount is set so as to satisfy a desired separation capability and to secure a junction breakdown voltage of about 10 V between the source / drain region 28a formed in a later step and the substrate 11 (FIG. 6).

Next, after an interpoly insulating film 24 made of an oxide film is formed on the entire surface, a photoresist film 35 is formed on the entire surface and patterned to cover the memory cell region 12 (FIG. 7). Next, using the photoresist film 35 as a mask, the interpoly insulating film 2 in the peripheral circuit region 13 is used.
4. Polysilicon film 23a and gate oxide film 22a
Are sequentially removed by etching to expose the surface of the substrate 11 (FIG. 8). Next, a gate oxide film 22b is formed in the peripheral circuit region 13.
After that, a polysilicon film and a tungsten silicide film are sequentially deposited on the entire surface and patterned, and a control gate 25 having a silicide film 27 formed thereon is formed in the memory cell region 12, and a peripheral circuit region 13 is formed.
A gate electrode 2 having a silicide film 27 formed thereon.
6 is formed. Thereafter, source / drain regions 28a and 28b are formed by ion implantation, and a predetermined process is performed to complete a semiconductor device (see FIGS. 1 and 2).

In this embodiment, the LOCOS oxide film 1
8a, 18b and 18c are formed, isolations 19 and 20 are formed by ion implantation, and then the photoresist film 3 used for forming the floating gate 23 is formed.
3 is used as a mask, and additional implantation is performed.
The second P ⁺ isolation 21 is formed immediately below the second LOCOS oxide films 18a and 18b. For this reason,
In the memory cell region 12, the LOCOS oxide film 18
Since the second P ⁺ isolation 21 is formed below the layer a by additional implantation in addition to the P ⁺ isolation 19, a sufficient separation capability can be secured even if the width of the LOCOS oxide film 18a is small, and miniaturization can be promoted. . In the peripheral circuit region 13, the width of the LOCOS oxide film 18c is relatively large, and the isolations 19, 20 are formed below the LOCOS oxide film 18c to such an extent that a desired junction breakdown voltage can be secured.
Is formed, and additional implantation is not performed, so that element isolation can be performed without lowering the junction breakdown voltage. As described above, the junction breakdown voltage in the peripheral circuit region 13 is prevented from lowering, the separation capability in the memory cell region 12 can be improved, and miniaturization can be achieved with high reliability.

In addition, since the additional implantation for forming the second P ⁺ isolation 21 uses the photoresist film 33 at the time of forming the floating gate 23 as a mask, it can be easily manufactured without increasing the photoengraving process. When the floating gate 23 is formed, the polysilicon film 23a is left over the entire surface of the peripheral circuit region 13 to perform the additional implantation. Therefore, the polysilicon film 23a is surely implanted only into the memory cell region 12 without being implanted into the peripheral circuit region 13. You.

Embodiment 2 FIG. In the first embodiment, the additional implantation for forming the second P ⁺ isolation 21 was performed using the photoresist film 33 as a mask (see FIG. 6), but the additional implantation was performed using the polysilicon film 23a as a mask. Is also good. FIG. 9 is a sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. As in the first embodiment, after the polysilicon film 23a is deposited, the polysilicon film 23a is etched using the photoresist film 33 as a mask to form the floating gate 23 made of the polysilicon film 23a in the memory cell region 12. Then, the polysilicon film 23a is left on the entire surface of the peripheral circuit region 13. Thereafter, as shown in FIG. 9, the photoresist film 33 is removed, and ions are implanted from above the substrate 11 using the polysilicon films 23 and 23a as a mask to form the second P ⁺ isolation 21.

In this embodiment, a semiconductor device similar to that of the first embodiment can be obtained, and the same effects as those of the first embodiment can be obtained. In addition, since the ion implantation for forming the second P ⁺ isolation 21 is performed after removing the photoresist film 33, the photoresist film 33 can be easily removed without impurities being implanted into the photoresist film 33. In addition, since the thickness of the ion implantation mask is reduced, impurities can be reliably and reliably implanted into the substrate 11 when oblique implantation having an angle of, for example, about 7 degrees is performed.

Embodiment 3 FIG. Next, a structure and a manufacturing method of a semiconductor device according to a third embodiment of the present invention will be described.
A description will be given based on FIG. As shown in FIG. 10, the LOCOS oxide film 18d in the memory cell region 12 is formed thinner than that in the peripheral circuit region 13 due to the difference in width. LOCOS oxide film 18 in memory cell region 12
d is formed to have a width of about 0.5 μm and a thickness of about 0.5 μm, for example, so that the peripheral circuit region 13 and the memory cell region 12 are formed.
LOCOS oxide films 18e, 18f located at the boundary with
Is formed, for example, with a width of about 1.0 μm and a thickness of about 1.0 μm in the same manner as in the first embodiment.
After the formation of the photoresist films 9 and 20, the photoresist film 3 used to form the floating gate 23 is formed in the same manner as in the first embodiment.
3 as a mask, additional implantation for forming the second P ⁺ isolation 21 is performed, for example, at an implantation energy of 200 Ke.
Perform at about V.

LOCOS oxide films 18d, 18e, 18f
The method for forming the above will be described below with reference to FIG. First,
A nitride film 36 is formed on a substrate 11 and a photoresist film 37 is formed.
A mask is used to form a nitride film 36 pattern (FIG. 11).
(A)) The LOCOS oxide film 1 is formed in the peripheral circuit region 13 including the boundary with the memory cell region 12 by the LOCOS method.
8e and 18f are formed. Here, the LOCOS oxide film 18f in the peripheral circuit region 13 is the same as the LOCOS oxide film 18e located at the boundary, and is not shown (FIG. 11).
(B)). Next, using the photoresist film 38 as a mask,
The nitride film 36 is patterned again (FIG. 11C), and the LOCOS is formed in the memory cell region 12 and the peripheral circuit region 13.
A thin LOCOS oxide film 18d is newly formed in the memory cell region 12 by applying the LOCOS method.
The oxide films 18e and 18f are formed to have a larger thickness (FIG. 11D). Thereafter, the nitride film 36 is removed.

As described above, the LOCO of the memory cell region 12 is
Since the S oxide film 18d is formed thin, additional implantation for the second P ⁺ isolation 21 formed immediately below the LOCOS oxide film 18d can be performed with low energy. Therefore, FIG.
0, the memory cell region 12 and the peripheral circuit region 13
Below the LOCOS oxide film 18e located at the boundary with
The second P ⁺ isolation 21 can be prevented from being formed due to the impurity implantation, and the junction breakdown voltage can be improved at the end of the peripheral circuit region 13 adjacent to the memory cell region 12. Further, since additional implantation can be performed with low energy, damage to the substrate 11 due to the implantation can be reduced, and the thickness of the photoresist film 33 used as the implantation mask can be reduced.
Dimensional controllability during patterning can be improved.

Embodiment 4 In the third embodiment, as in the second embodiment, additional implantation for forming the second P ⁺ isolation 21 is performed using the polysilicon films 23 and 23a as a mask after removing the photoresist film 33. FIG. 12 shows the manufacturing method. Accordingly, the same effect as in the third embodiment is obtained, and similarly to the second embodiment, the removal of the photoresist film 33 is facilitated, and the additional implantation by oblique implantation can be performed with high reliability. Further, since additional implantation can be performed with low energy, implantation damage to the surfaces of the polysilicon films 23 and 23a can be reduced, and the reliability of the interpoly insulating film 24 formed in a later step can be improved.

Embodiment 5 Next, a structure and a manufacturing method of a semiconductor device according to a fifth embodiment of the present invention will be described.
This will be described with reference to FIG. As in the third embodiment, the LOCOS oxide films 18d, 18e, and 18f are formed so that the LOCOS oxide film 18d in the memory cell region 12 becomes thin. Thereafter, isolations 19 and 20 are formed, and a gate oxide film 22a and a polysilicon film 23 are formed.
The steps up to the formation of a are performed in the same manner as in the third embodiment. Next, as shown in FIG. 13, a photoresist film 33a is formed on the entire surface of the polysilicon film 23a and patterned.
Using the photoresist film 33a as a mask, the underlying polysilicon film 23a is etched to form the memory cell region 1
2, a gate electrode 23b is formed in a part of the peripheral circuit region 13, and a polysilicon film 23c is left in the remaining part of the peripheral circuit region 13 so as to cover the surface. Subsequently, additional implantation for forming the second P ⁺ isolation 21 is performed from above the substrate 11 to just below the LOCOS oxide film 18d in the memory cell region 12 using the photoresist film 33a as a mask. At this time,
LOC of the memory cell region 12 as in the third embodiment.
Since the thickness of the OS oxide film 18d is small, implantation can be performed with low energy. In the peripheral circuit region 13, even at the opening of the photoresist film 33a, impurities do not reach the lower layers of the thick LOCOS oxide films 18e and 18f.

Thereafter, when an interpoly insulating film 24 is formed and a control gate 25 is formed, a portion of the peripheral circuit region 13 where the polysilicon film 23c remains is formed.
The gate electrode 26 is formed at the same time (not shown).

In this embodiment, the memory cell region 12
LOCOS oxide film 18d is formed thinly, a gate electrode 23b is simultaneously formed in a part of the peripheral circuit region 13 when the floating gate 23 is formed, and the photoresist film 33a used for forming the floating gate 23 and the gate electrode 23b is used as a mask. Of the memory cell region 12
A second P ⁺ isolation 21 is formed directly below the OCOS oxide film 18d by additional implantation. Since the additional implantation can be performed with low energy, the second P ⁺ isolation 2 is formed under the LOCOS oxide films 18 e and 18 f in the peripheral circuit region 13.
1, the gate electrode 23b can be formed at the same time as the floating gate 23 is formed. Therefore, in the peripheral circuit region 13, two types of gate electrodes 23b, 26, which are formed simultaneously when the floating gate 23 is formed and a gate electrode 26 formed simultaneously when the control gate 25 is formed, are provided with photolithography. A semiconductor device that can be easily formed without increasing the number of steps and has improved design flexibility can be obtained. Note that all the gate electrodes 23b in the peripheral circuit region 13 can be formed simultaneously when the floating gate 23 is formed.

Embodiment 6 FIG. In the fifth embodiment, as in the fourth embodiment, additional implantation for forming the second P ⁺ isolation 21 is performed by the photoresist film 33a.
Is removed, the polysilicon film 23a (23, 23b,
23c) may be performed using a mask, and the manufacturing method is shown in FIG. This has the same effect as that of the fifth embodiment, facilitates removal of the photoresist film 33a similarly to the fourth embodiment, makes it possible to perform additional implantation by oblique implantation with high reliability, and to improve the polysilicon film. Injection damage to the surface of the 33a can be reduced.

[0034]

As described above, according to the present invention, the second isolation diffusion layer is formed by the LO in the memory cell region.
Since it is provided just below the COS oxide film, a reduction in junction breakdown voltage in the peripheral circuit region can be prevented, the isolation capability in the memory cell region can be improved, and a highly reliable semiconductor device suitable for miniaturization can be obtained.

According to the present invention, the LOCOS oxide film in the memory cell region is thinner than that in the peripheral circuit region beyond the film thickness difference caused by the difference in width, so that the second isolation diffusion layer is formed. Low-energy ion implantation ensures LOC in the memory cell area
The semiconductor device can be formed only directly under the OS oxide film, and a highly reliable semiconductor device can be obtained.

According to the present invention, the second isolation diffusion layer is formed by ion implantation using the resist mask at the time of patterning the floating gate. For this reason, a highly reliable semiconductor device suitable for miniaturization, which can prevent a decrease in junction breakdown voltage in the peripheral circuit region and improve the isolation capability in the memory cell region, can be easily manufactured.

According to the invention, the second isolation diffusion layer is formed by ion implantation using the polysilicon film serving as a floating gate as a mask after removing the resist mask. Therefore, it is possible to easily manufacture a highly reliable semiconductor device suitable for miniaturization, which can prevent a decrease in junction breakdown voltage in the peripheral circuit region and improve the separation capability in the memory cell region, and can easily remove the resist film. In addition, the reliability of ion implantation is improved by reducing the thickness of the implantation mask.

Further, according to the present invention, the LOCOS method is first applied to the peripheral circuit area, and then the LOCOS method is applied again to the peripheral circuit area and the memory cell area.
An OS oxide film is formed. For this reason, the LOCOS oxide film in the memory cell region can be easily formed thinner than that in the peripheral circuit region beyond the film thickness difference caused by the difference in width, and the second isolation diffusion layer can be formed by low energy ion implantation. LOC in the memory cell area
A highly reliable semiconductor device suitable for miniaturization, which can be formed only under the OS oxide film, prevents a decrease in junction breakdown voltage in the peripheral circuit region, and improves the isolation capability in the memory cell region, can be easily manufactured. .

Further, according to the present invention, when patterning the floating gate, the polysilicon film is left on the entire surface in the peripheral circuit region, and then the second isolation diffusion layer is formed. A highly reliable semiconductor suitable for miniaturization, which can be surely formed just under the LOCOS oxide film in the memory cell region, prevents a decrease in junction withstand voltage in the peripheral circuit region, and improves the isolation capability in the memory cell region. The device can be easily manufactured.

According to the present invention, at the time of patterning the floating gate, at least a part of the peripheral circuit region is formed by patterning the gate electrode of the transistor. A highly reliable semiconductor device suitable for miniaturization, which can improve the isolation capability in the cell region, can be easily manufactured, and the degree of freedom in design is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a structure of the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing one step of a method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a sectional view showing a structure and a manufacturing method of a semiconductor device according to a third embodiment of the present invention;

FIG. 11 is a sectional view showing a step of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a sectional view illustrating a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view showing a structure and a manufacturing method of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 14 is a sectional view illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

11 semiconductor substrate, 12 memory cell area, 13 peripheral circuit area, 18a, 18b, 18c, 18d, 18e,
18f LOCOS oxide film, 19, 20 isolation diffusion layer, 21 second isolation diffusion layer, 2
3 floating gate, 23a polysilicon film,
23b gate electrode, 30, 32, 34 ion implantation,
33, 33a Resist film.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/788 29/792

Claims (7)

[Claims] 1. A LOCOS oxide film for device isolation, comprising a memory cell region of a nonvolatile memory having a floating gate and a peripheral circuit region on a semiconductor substrate.
Providing an isolation diffusion layer below the OCOS oxide film in both the memory cell region and the peripheral circuit region;
A semiconductor device comprising a second isolation diffusion layer provided only under the LOCOS oxide film in the memory cell region. 2. The semiconductor device according to claim 1, wherein the LOCOS oxide film in the memory cell region is thinner than that in the peripheral circuit region, exceeding a film thickness difference caused by a difference in width of the LOCOS oxide film. Semiconductor device. 3. A first step of forming a LOCOS oxide film on a semiconductor substrate, a second step of forming an isolation diffusion layer by ion implantation, and forming a polysilicon film serving as a floating gate via a gate oxide film. A third step of patterning the floating gate in the memory cell region using the resist mask after the deposition, and a fourth step of forming a second isolation diffusion layer by ion implantation using the resist mask. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising: 4. A first step of forming a LOCOS oxide film on a semiconductor substrate, a second step of forming an isolation diffusion layer by ion implantation, and forming a polysilicon film serving as a floating gate via a gate oxide film. After the deposition, a third step of patterning the floating gate in the memory cell region using a resist mask, removing the resist film, and forming a second isolation diffusion layer by ion implantation using the polysilicon film as a mask 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a fourth step. 5. A method of forming a LOCOS oxide film in a first step, wherein a LOCOS method is first applied to a peripheral circuit region, and then a LOCOS method is applied again to the peripheral circuit region and the memory cell region.
The method according to claim 3, wherein the method is performed by applying an OS method. 6. A patterning of a floating gate in a third step, in which a polysilicon film is left on the entire surface in a peripheral circuit region, and after forming a second isolation diffusion layer, the polysilicon film in the peripheral circuit region is formed. 4. The method according to claim 3, wherein the silicon film is removed.
6. The method for manufacturing a semiconductor device according to any one of claims 1 to 5. 7. The method of manufacturing a semiconductor device according to claim 5, wherein at the time of patterning the floating gate in the third step, the gate electrode of the MOS transistor is formed by patterning at least a part of the peripheral circuit region. Method.