JPH1186737A - Plasma display panel and display device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress high voltage generated between address electrodes and to prevent the occurrence of an unintentional abnormal discharge by providing a conductor section made of a conductive member in at least a part of the region of the face on the opposite side to the face formed with an address electrode group of an insulating substrate. SOLUTION: A conductive layer 4 of an ITO film is formed in nearly the entire region except for the external connecting terminals 5 (5-1, 5-2, 5-3,...) of an address electrode group 3 on the face (back face) on the opposite side to the face formed with the address electrode group 3 of a glass insulating substrate 2. A capacity is formed by the address electrode group 3 and the conductor layer 4 across the glass insulating substrate 2. The positive electric charges induced on the electrode lines of the address electrode group 3 are restrained by the negative electric charges, generated on the surface of the conductor layer 4 by the polarization of the glass insulating substrate 2. The biasing of the positive electric charges generated on the address electrode group 3 is suppressed and removed, and the occurrence of a high voltage between the adjacent address electrodes 3-1, 3-2,... can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel used for an information processing terminal, a flat panel type, a wall-mounted television, and the like, and a display device using the same. In particular, the present invention relates to a plasma display panel and a display device using the same. Related to the structure to be operated.

[0002]

2. Description of the Related Art As a conventional plasma display device, there is, for example, a device disclosed in Japanese Patent Application Laid-Open No. Hei 5-190999. As shown in FIG. 5, the three-electrode surface discharge AC type has a configuration of a capacitance circuit in which three electrodes of X, Y, and address are connected by a wiring capacitance. At this time, the ground terminal in the drive circuit does not exist on the panel.
The discharge light emission of the X and Y electrodes during the sustain period is basically based on an AC operation in which an anode and a cathode serve as an anode. On the other hand, the ground seen from the address electrode corresponds to the other X and Y electrodes.

[0003]

In the above-mentioned conventional plasma display device, due to the above-mentioned structural characteristics,
The ground for the panel is apparently very weak, and it has been experimentally confirmed that a high voltage, which is considered to be related to the weakness of the ground, is generated between the address electrodes, and an unintended abnormal discharge may occur between the address electrodes. ing.

When an abnormal discharge occurs, there is a possibility that the address driving IC is destroyed by the discharge current. For this reason, in order to guarantee the stable operation of the plasma display panel, it is necessary to increase the withstand voltage of the address driving IC, which is one of the causes of raising the manufacturing cost. Further, when the abnormal discharge occurs, the dielectric layer of the plasma display panel is destroyed, which causes a shortened product life.

An object of the present invention is to provide a plasma display panel capable of suppressing a high voltage generated between the address electrodes of the plasma display panel and preventing the occurrence of the unintended abnormal discharge, and a plasma display panel using the same. To provide a display device.

Another object of the present invention is to prevent the address driving IC for driving the plasma display panel from being destroyed and to ensure a stable operation.

Another object of the present invention is to provide an address drive IC for driving a plasma display panel which does not need to have a high withstand voltage, and to provide a drive IC at low cost.

Still another object of the present invention is to prevent dielectric breakdown of a dielectric layer of a plasma display panel and to secure product life and reliability.

[0009]

In a conventional plasma display panel display device, as shown in FIG. 6, a drive circuit for supplying a pulse voltage waveform to three electrodes has a common ground, but each electrode has a common circuit. It is connected to the ground by stray capacitance.

The inventor of the present application has analyzed the operating conditions for each electrode structure paying attention to the existence of the stray capacitance, and found that the stray capacitance Cag associated with the address electrode structure is a special phenomenon for the address drive circuit, especially the above-mentioned phenomenon. A new mechanism has been found to facilitate such an abnormal discharge phenomenon. Hereinafter, this will be described in detail.

In a plasma display panel, wall charges formed when the panel is driven are formed on each electrode according to a potential distribution of a driving waveform. The address electrode is
Since the period during which the X and Y electrodes serve as anodes is long with respect to the driving conditions during the sustain period, positive (ion) wall charges are likely to be formed on the “true electrodes” inside the cell. The “true electrode” here means the surface of a dielectric layer (including a phosphor) formed on the address electrode line, and is hereinafter referred to as a dielectric surface electrode.

The formation of the wall charge (positive charge) induces a negative charge on the address electrode surface on the dielectric layer side at a time level of the time constant τ of the address electrode (line), and at the same time, the opposite electrode back surface. Generates a positive charge in an amount equal to the negative charge. The distribution of negative charges is restricted by wall charges (positive charges),
Positive charges generated on the back surface of the opposite electrode follow the potential distribution with respect to the ground due to the coupling with the stray capacitance. Since the ground of the panel is weak, the positive charge on the back surface of the electrode takes a distribution that depends particularly on the structure and arrangement of the address electrodes.

FIG. 7A shows a case where a positive charge is formed on the back surface of the address electrode (line). However, in this case, the address electrode lines are alternately taken out from both upper and lower sides in order to increase the pitch between terminals.

The address electrode has a high voltage (V = V) due to the concentration of the positive charge Q at the tip of the electrode (FIG. 7B: a cross-sectional model diagram along the line AA 'in FIG. 7A) and the stray capacitance C with respect to the ground.
Q / C), but the voltage is low on the extraction side of the two electrode lines adjacent to the electrode tip (opposite the tip). Therefore, a high voltage is easily generated between the adjacent address electrodes, and an unintended discharge (see arrows in FIGS. 7A and 7B) occurs.

The dielectric breakdown voltage between the address electrodes at this time is, for example, the dielectric strength of soda glass: 10 kv / m
m, gap length between adjacent address electrode lines:
If 0.2 mm is used, it becomes 2 kv. It is known that the actual breakdown voltage is further reduced by the presence of defects such as pinholes and electrode protrusions in the dielectric.

Experiments show that the discharge current flowing with the discharge flows into the drive IC via the adjacent address electrode lines and also from the X and Y electrodes to the address electrode lines, forming a closed loop. Has been confirmed.

Further, the induced voltage (positive charge) for generating a discharge depends on the time constant τ of the address electrode line, and X, Y
Resonates with a harmonic component such as a sustain voltage waveform of the electrode (line). For this reason, a voltage distribution is generated according to a line model in which the ends of the address electrodes (lines) are open ends. It has been experimentally confirmed that the unintended discharge described above occurs at a specific position other than the end portion (a position where the potential difference becomes large).

On the other hand, the discharge energy depends on the amount of positive charges induced on the back surface of the address electrode (line).
Since it has been experimentally confirmed that the address driving IC may be destroyed, the above-mentioned discharge energy is sufficient for the destruction of the driving IC.

The high voltage generated between the address electrodes is shown in FIG.
This will be described using an equivalent circuit model shown in FIG.

The wall charge Qw formed on the dielectric surface electrode, which is the "true electrode" of the address electrode, is given by application of a DC voltage Vi (virtual voltage) in an equivalent circuit. The wall charge Qw generates induced voltages Va and Vb for two capacitors Ca and Cb connected in series on the circuit. Here, the capacitances Ca and Cb are the dielectric capacitance between the dielectric surface electrode (“true electrode”) and the address electrode (line), and the stray capacitance Cb between the address electrode (line) and the common ground of the drive circuit.
(Equivalent to Cag in FIG. 6). Ri-1, Ri, Ri + 1
Indicates the equivalent resistance of the driving IC connected to the address electrode (line).

The relationship between the wall charge Qw and the capacitances Ca and Cb at this time is shown below.

Qw = Ca · Va = Cb · Vb (Equation 1) where Vi = Va + Vb.... (2) From the panel structure, the stray capacitance Cb is sufficiently smaller than the dielectric capacitance Ca, so that Ca ≫ Cb....... (Equation 3) From the above equations (1) and (3), Va Ｖ Vb (Equation 4) Therefore, the wall charge Qw is satisfied under the condition of the above equation (3). (FIG. 8 i-th line,
When the charge concentration: n times, n≫1) is added, the positive charge Qw '
Indicates that the induced voltage Vb ′ becomes very large with respect to the induced voltage Va. At this time, the adjacent address electrodes (i
The high voltage Vo generated between (−1, i + 1st line) is given by: Vw = n · Qw = Cb · Vb ′ (Equation 5) '= N · (Ca / Cb) · Va = 〜Vo …………………………… (Equation 6) Here, the symbol “= 〜” means that the values on both sides are substantially equal.

The induced voltage Va is, for example, according to a potential distribution generated by a sustain discharge between the X and Y electrodes.
Due to the symmetry of the electrode structure, 7 which is about half of the sustain voltage
Expected to be 5-100v. Further, the measurement results of the dielectric capacitance Ca and the stray capacitance Cb of the actual panel confirm that there is a difference of one digit or more.

From the above, the induced voltage Vb 'due to the wall charge Qw is obtained.
Is easily 1 from the relationship between the charge concentration and the capacitance ratio (Ca / Cb).
Since it exceeds kv or more (exceeds the above-mentioned breakdown voltage), it is considered that an unintended discharge is likely to occur.

According to the present invention, in order to solve the above-mentioned problem of the present invention, that is, to suppress a high voltage generated between address electrodes, a plasma display panel includes:
Provided is a structure for eliminating a bias with respect to a positive charge distribution on an address electrode generated by wall charges Qw. This deviation is caused by the weak ground of the panel as described above, and depends on the structure and shape of the address electrode (line). The means for removing the bias of the positive charge distribution shown in FIG. 7A basically includes disposing a conductor plane or conductor pattern near an address electrode (line) via a dielectric material, (Line) and the above-mentioned conductor plane or conductor pattern to form a new capacitance.

When the address electrode line is handled by a line model, a means for reducing the characteristic impedance of the line and suppressing the generation of a high voltage by forming a new capacitance is provided.
However, the above-described conductor plane or conductor pattern is arranged on the opposite side of the dielectric surface electrode with respect to the address electrode (line).

As shown in FIG. 9, positive charges Q + (wall charges Qw
(Approximately equal to the above), the negative charge Q- attracting the polarization due to the dielectric is generated in the conductor plane or the conductor pattern to suppress or prevent the movement of the charge which causes the bias. . In order to increase the suppressing force and the blocking force, the capacitance of the dielectric formed by the address electrode (line) and the above-mentioned conductor plane or conductor pattern may be increased. However, it is necessary not to affect the driving conditions of the address electrodes (lines). That is, the capacitance (Cb) formed by the above-mentioned conductor plane or conductor pattern and one address electrode line is made somewhat smaller than the capacitance (Co) between adjacent address electrodes.

When the negative charge Q- tends to cause a bias with respect to the shape or structure of the conductor plane or the conductor pattern, the positive charge cannot be efficiently restrained, so that the bias (movement) of the charge is prevented. The effect of suppressing and blocking is reduced. In order to prevent this, the above-described conductor plane or conductor pattern is finely arranged and formed. In particular, a large number of fine line patterns arranged and formed perpendicular to the address electrode lines suppress the bias of the positive charges Q + in the direction of the address electrode lines and also reduce the bias of the negative charges Q-. It is also effective.

At this time, the positive charges simultaneously generated in the conductor plane or the conductor pattern generate a constant induced voltage with respect to the common ground via the stray capacitance.
Since the above-mentioned conductor plane or conductor pattern is floating with respect to the ground, there is no problem unlike the address electrode line.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a panel rear substrate of a plasma display panel to which the present invention is applied will be described with reference to FIGS.

FIG. 1 is a plan view of a panel back substrate 1 of a plasma display panel.

An address electrode group 3 (3-1, 3-2, 3-3,...) Composed of a large number of electrode lines is formed on one surface of the glass insulating substrate 2, and is alternately taken out from both upper and lower sides. It is. On the other surface (back surface) of the glass insulating substrate 2, a conductor layer 4 of an ITO film was used, except for external connection terminals 5 (5-1, 5-2, 5-3,...) Of the address electrode group 3. It is formed in almost the entire area. As a result, a capacitance is formed between the address electrode group 3 and the conductor layer 4 with the glass insulating substrate 2 interposed therebetween.

FIG. 2 is a sectional view taken along line AA ′ of FIG.

Each electrode line 3- (i) of the address electrode group 3
The positive charge Q + 6 induced in -1), 3- (i), 3- (i + 1),... Is restricted by the negative charge Q-7 generated on the surface of the conductor layer 4 by the polarization of the glass insulating substrate 2. Is done. For this reason,
The bias of the positive charges Q + 6 generated in the address electrode group 3 is suppressed and eliminated, thereby preventing a high voltage from being generated between adjacent address electrodes.

The capacitor 9- (i) formed between the electrode line 3- (i) and the conductor layer 4 is connected to the adjacent electrode lines 3- (i-1) and 3- (i + 1). Are smaller than the capacitances 8- (i-1) and 8- (i) formed between them, and are arranged such that the load condition does not change with respect to the drive IC of the address electrode group 3. However, in order to increase the binding force of the positive charge Q + 6, the capacitance 9- (i) may be set to be larger under the above conditions.

On the other hand, the conductor layer 4 does not need to be particularly transparent, and may be formed of a thick conductor such as Cu or Al, or a conductor sheet. When a conductor sheet is used, the capacitance 9- (i) can be further increased by making the adhesive layer conductive. The shape of the conductor layer 4 is basically based on a conductor plane formed of a solid layer, but the through holes (openings) are formed uniformly in consideration of the effect on the capacitance 9- (i), or A configuration in which a lattice is formed may be used.

Another embodiment to which the present invention is applied will be described with reference to FIG. FIG. 3 shows a cross-sectional structure when cut perpendicular to the address electrode group 14 on the panel back substrate 17 of the plasma display panel as in FIG.

In this embodiment, a base insulating film 11 of SiO ₂ is formed on a glass insulating substrate 10,
The conductor layer 12 of the TO film is formed. On the conductor layer 12, a dielectric layer 13, an address electrode group 14, and a dielectric layer (including a phosphor layer) 15 are sequentially formed. In the present embodiment, a structure is provided in which the conductive layer 12 is brought closer to the address electrode group 14 without the glass insulating substrate 10 therebetween.

According to the above structure, the electrode line 14- (i)
16- (i) formed with respect to the conductor layer 12 with respect to
And the binding force of the positive charge Q + 6 is increased under appropriate load conditions for the drive IC of the address electrode group 14. When adjusting the capacitance 16- (i), in addition to changing the material (relative permittivity) and structure (layer thickness) of the dielectric layer 13, a through-hole (opening) portion or the like is formed in the solid layer area of the conductor layer 12. A method of forming a grid uniformly is used.

Another embodiment of the present invention will be described with reference to FIG. FIG. 4 is a plan view of the panel rear substrate 18 of the plasma display panel.

In this embodiment, after a SiO ₂ base insulating film (omitted) is formed on a glass insulating substrate 19, a conductor pattern layer 20 (20-1, 2-2) composed of a large number of fine wire patterns is formed.
0-2, 20-3,...). Conductor pattern
A dielectric layer (omitted), an address electrode group 21 (21-1, 21-2, 21-3,...), And a dielectric layer (including a phosphor layer) (omitted) are formed on the insulating layer 20. They are formed in order. At this time, the conductor pattern layer 20 composed of a thin wire pattern is arranged perpendicular to the address electrode group 21 and the external connection terminals 22 (22-1, 22-22) of the address electrode group 21.
2, 22-3,...). The conductor pattern layer 20 is composed of a large number of separated fine wire patterns.
In this case, the conductor pattern layer 2 can be compared with the solid layer.
Since the bias of the negative charge Q- (omitted) generated in 0 can be suppressed and removed, the bias (omitted) of the positive charge Q + that generates the high voltage is effectively removed.

The shape (width, pitch, etc.) of the conductor pattern layer 20 with respect to the fine line pattern is determined by the capacitance formed between the conductor pattern layer 20 and the address electrode group 21 via a dielectric layer (omitted). Are set so as not to affect the driving conditions of the address electrode group 21. Although the conductor pattern layer 20 is formed on the same surface as the surface on which the address electrode group 21 is formed with respect to the glass insulating substrate 19, the conductor pattern layer 20 may be formed on the opposite surface. In this case, other methods such as attaching a copper foil pattern can be used.

As another embodiment of the present invention, a display device including the plasma display panel of the above embodiment will be described. Here, a case will be described as an example in which the substrate shown in FIGS. 1 and 2 is used as a panel rear substrate of a plasma display panel.

FIG. 10 shows an electrode line arrangement structure of the plasma display panel 619 in this embodiment.
X electrode 620 and Y electrode 621 formed on panel front substrate
1 shows a state in which address electrodes (hereinafter, abbreviated as A electrodes) 3 formed on the panel rear substrate according to the embodiment of FIG. 1 are orthogonal to each other.

In the case of a VGA panel for driving as a (Y) scan electrode, 480 Y electrodes 621 from 621-1 to 621-480 are formed excluding dummy electrodes and the like. On the other hand, in the case of the X electrode 620, all the Y electrodes 621-1 to 621-48 are simultaneously driven as a common electrode.
480 electrode lines corresponding to 0 are electrically connected and formed. The A electrode 3 addresses 640 pixels in the VGA panel and 1920 (RGB) in order to address RGB display.
× 3) 1920 from 3-1 to 3-1920 for the cell
A book is formed. The extraction terminals of the A electrode 3 are formed on both sides of the plasma display panel 619.

FIG. 11 shows a sectional structure taken along line BB 'of FIG. 10 on the A electrode 3 of the plasma display panel 619.

Focusing on the one cell region 24 in the Y scan direction, the protective layer 36 made of the MgO film is removed from the transparent glass substrate 28.
11 and the panel back substrate 1 including the glass substrate 2 on which the conductor layer 4 is formed to the dielectric layer 35-2 are separated from each other by partition walls (in FIG. Although not shown, they are arranged to face each other across a partition height h (27) according to the following sectional view of FIG. The partition height h (27) is 1 in consideration of the phosphor thickness.
It is often optimized at 00 to 200 μm.

In the panel front substrate 25, a transparent SiO ₂ base film 29-1 is formed on a transparent glass substrate 28, and a transparent ITO film constituting an X electrode 620 and a Y electrode 621 is formed thereon. 32-1, 32-2 and opaque Cr
/ Cu / Cr metal laminated films 33-1 and 33-2 are formed. The firing voltage Vxy between the X electrode 620 and the Y electrode 621 mainly depends on the length g (34) of the discharge gap formed by the ITO films 32-1 and 32-2. On the X electrode 620 and the Y electrode 621, a dielectric layer 35-1 of about 10 to 20 μm is formed by a thick film process in order to accumulate wall charges and secure insulation between the electrodes. Furthermore,
A protective layer 36 of an MgO film having a large two-electron emission coefficient γ and excellent sputter resistance is formed thereon. In particular, Mg
In order to reduce the film stress of the O film, the dielectric layer 35 may be formed in a multilayer structure in consideration of the material and process conditions.

In the panel back substrate 1, a transparent SiO ₂ base film 29-2 is formed on the glass substrate 2 on which the conductor layer 4 described in the embodiment of FIG. A electrode 3 made of an opaque Cr / Cu / Cr metal laminated film and a dielectric layer 35-2 formed by a thick film process.
Are sequentially formed. On the panel back substrate 1 on which the dielectric layer 35-2 is formed, a not-shown partition (shown in a cross-sectional view of FIG. 12) is formed, and further, on the side of the partition and on the surface of the dielectric layer 35-2 where the partition is not arranged. The phosphor 39 required for display light emission is formed.

Panel back substrate 1 formed up to phosphor 39
And the panel front substrate 25 are integrally assembled so that a three-electrode cell structure is formed uniformly and accurately over the entire surface of the panel, and plasma is sealed by airtight sealing in which a constant Ne-Xe gas (200 torr) is sealed. Display panel 619
Is produced.

A pulse voltage is applied between the two electrodes of the X electrode 620 and the Y electrode 621, and the ultraviolet light 40 generated by the sustain discharge excites the phosphor 39 to emit visible light.

FIG. 12 shows CC ′ drawn on the Y electrode 621 of the plasma display panel 619 in FIG.
FIG.

Focusing on the one pixel area 41 in the address direction, the discharge spaces 42-1, 42-2, 4
2-3, the panel front substrate 25 including the transparent glass substrate 28 to the protective layer 36 of the MgO film;
From the glass substrate 2 formed on the back surface to the dielectric layer 35-2
Panel back substrate 1 including the dielectric partition walls 43-1, 43-2, 43 serving also to secure the discharge space 42.
-3 and 43-4, and are opposed to each other with a partition height h (27) therebetween.

FIG. 13 shows the plasma display panel 6.
19 shows an example of a block configuration of a display device for driving the display device 19.

The basic configuration of the display device is given by a panel, a drive circuit, a control circuit, and a power supply circuit.
A plasma display panel 619 in which display lines composed of 0, Y electrodes 621 and A electrodes 3 are formed, and a light emitting display by a write discharge and a sustain discharge (sustain discharge) between the electrodes using wall charges for the display lines. A drive circuit for applying various drive voltage waveforms for performing the control, a control circuit for transferring display data to control the drive circuit, and a DC / DC converter for generating various internal voltages required for the drive circuit. Power supply circuit.

The drive circuit includes X and Y sustain pulse generators 44-1 and 44-2, a scan driver LSI row 45 using a monolithic LSI driver, and address driver LSI rows 46-1 and 46-2. . The scan driver LSI array 45 adopts a floating method of shifting a reference voltage to overlap the Y sustain pulse generator 44-2, and transmits a control signal through a photocoupler 47.

The control circuit 48 functioning as a control circuit is composed of a gate array and a frame memory.
The DC / DC converter 49 is connected to the sustain voltage V.
Various internal voltages Vwi and Vaj required for the drive waveform are generated based on s.

According to the display device of the present embodiment using the plasma display panel having the panel back substrate 1 according to the present invention as described above, the high voltage generated between the address electrodes of the plasma display panel is suppressed. Unnecessary discharge can be prevented. Therefore, according to the display device of the present embodiment, it is possible to prevent the address driving IC from being destroyed and to ensure a stable operation. Further, an address driving IC
It is not necessary to increase the breakdown voltage of the driving IC, and the cost of the driving IC can be reduced. Further, it is possible to prevent dielectric breakdown of the dielectric layer of the plasma display panel, and to ensure product life and reliability.

In this embodiment, the case where the panel rear substrate shown in FIGS. 1 and 2 is used has been described as an example, but the panel rear substrate having the structure shown in FIG. 3 or FIG. Needless to say, it can be used for

[0060]

According to the present invention, a conductor plane or a conductor pattern is arranged near an address electrode (line) via a dielectric, and the address electrode (line) and the conductor plane or the conductor pattern described above are arranged. By forming a new capacitor with the negative electrode, the bias is removed from the positive charge distribution on the address electrode generated by the wall charge Qw, and there is an effect of suppressing a high voltage generated between the address electrodes.

[Brief description of the drawings]

FIG. 1 is a plan view of a panel rear substrate 1 of a plasma display panel according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a cross-sectional configuration taken along line AA ′ of FIG.

FIG. 3 is another embodiment of the present invention, and is an explanatory view showing a cross-sectional configuration when the address electrode group 14 of a panel rear substrate 17 of the plasma display panel is cut perpendicularly.

FIG. 4 is another embodiment of the present invention, and is a plan view of a panel rear substrate 18 of the plasma display panel.

FIG. 5 is an explanatory diagram showing an equivalent circuit model of a three-electrode surface discharge AC type plasma display panel and its driving circuit.

FIG. 6 is an explanatory diagram showing an equivalent circuit model when stray capacitance is considered in FIG. 5;

FIG. 7A is a plan view when positive charges are formed on the back surface of the address electrode line of the plasma display panel. FIG. 7B is an explanatory diagram showing a cross-sectional configuration taken along line AA ′ of FIG. 7A.

FIG. 8 is an explanatory diagram showing an equivalent circuit model for obtaining a high voltage generated between address electrodes.

FIG. 9 is an explanatory diagram showing an equivalent circuit model showing a solution of the present invention.

FIG. 10 is an explanatory diagram showing an electrode structure in one embodiment of the plasma display panel according to the present invention.

FIG. 11 is an explanatory view showing a cross-sectional structure taken along line BB ′ of FIG. 10;

FIG. 12 is an explanatory view showing a cross-sectional structure taken along the line CC ′ of FIG. 10;

13 is a block diagram showing a configuration example of a display device using the plasma display panel of FIG.

[Explanation of symbols]

 1, 17, 18: panel back substrate 2, 10, 19: glass insulating substrate 3, 14, 21: address electrode group 4, 12, conductor layer 20: conductor pattern layer 5, 22: external connection terminal 6: positive Charge 7: negative charge 9, 16: capacitance formed.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shoji Ishigaki 4-6-6 Kanda Surugadai, Chiyoda-ku, Tokyo Inside the Home Appliances and Information Media Business Division, Hitachi, Ltd. 6-chome Hitachi Electronics Co., Ltd. Home Appliances and Information Media Business Headquarters (72) Keizo Suzuki Inventor 4-6-chome Kanda Surugadai, Chiyoda-ku, Tokyo Hitachi, Ltd. Home Appliances and Information Media Business Headquarters

Claims (9)

[Claims] 1. A plasma display panel in which a panel front substrate having a display electrode group and a panel rear substrate having an address electrode group are combined, wherein the panel rear substrate has the address electrode group formed on one surface. And a conductor portion made of a conductive member provided on at least a part of a surface of the insulating substrate opposite to a surface on which the address electrode group is formed. Plasma display panel. 2. A plasma display panel comprising a panel front substrate having a display electrode group and a panel rear substrate having an address electrode group, wherein the panel rear substrate has the address electrode group formed on one side. And an electrically conductive member provided between the address electrode group and at least a part of a surface of the insulating substrate on the same side as the side on which the address electrode group is formed. A plasma display panel, comprising: a conductor portion provided with a conductive layer; and a dielectric layer provided between the conductor portion and the address electrode group. 3. The conductor plate according to claim 1, wherein the conductor portion is a conductor plane formed of a planar conductive member covering at least a part of the surface of the insulating substrate.
The plasma display panel as described in the above. 4. A capacitance between two adjacent electrode lines of the address electrode group is larger than a capacitance formed by one electrode line of the address electrode group and the conductor plane. 3. The plasma display panel according to 3. 5. The plasma display panel according to claim 3, wherein a plurality of openings are formed in said conductor plane. 6. The conductor section is a conductor pattern formed by arranging a plurality of conductive strips arranged substantially parallel to each other without conduction and substantially perpendicular to the address electrode group. The plasma display panel according to claim 1 or 2, wherein: 7. A capacitance between two adjacent electrode lines of said address electrode group is larger than a capacitance formed by one electrode line of said address electrode group and said conductor pattern. Item 7. A plasma display panel according to item 6. 8. The method according to claim 1, wherein the conductor is formed by bonding a member made of a conductive member to the insulating substrate via a conductive adhesive layer. Plasma display panel. 9. A plasma display panel in which a panel front substrate having a display electrode group and a panel rear substrate having an address electrode group are combined, and the display electrode group and the address electrode for causing the plasma display panel to emit light. 9. A display device comprising: a drive circuit for supplying a predetermined drive voltage waveform to a group; wherein the plasma display panel is one of claims 1 to 8.