JPH118612A - Clock extract circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock extract circuit by which the phase of an extracted clock pulse is adjusted over a wide range. SOLUTION: A leading edge point differentiation circuit 4 that differentiates a leading edge of input data Sin and a trailing edge point differentiation circuit 5 are connected in parallel in the clock extract circuit 1, a monostable multivibrator 6 and a trailing change point differentiation circuit 8 are connected sequentially to the leading change point differentiation circuit 4 and a monostable multivibrator 7 and a trailing change point differentiation circuit 9 are connected sequentially to the trailing change point differentiation circuit 5. Through the constitution above, a phase adjustment range of an extracted clock pulse Sout is extended and a stable clock pulse is extracted without being affected by input data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock extracting circuit, and more particularly to a clock extracting circuit for extracting a clock pulse from received data in a signal receiving circuit of an optical transmission device in the field of optical communication.

[0002]

2. Description of the Related Art Conventionally, in a signal receiving system of an optical transmission apparatus, in order to regenerate an optical signal which has been reduced in level after passing through an optical fiber and which has been distorted, an electric signal converted photoelectrically is converted by an equalizing amplifier. Waveform shaping (Reshaping)
After extracting a clock pulse synchronized with the input data by a clock extraction circuit (Retiming), discriminating reproduction (Regenerating) is performed.
An optical receiver having a function is used.

In such a clock extraction circuit of an optical receiver, it is necessary to always perform identification and reproduction at an optimum identification point for various bit rates. For this purpose, means for optimizing a clock phase and a pulse width are provided. Have been. For example, a clock extraction circuit disclosed in Japanese Patent Publication No. H8-4261 includes a clock pulse phase adjusting means for punching out input data at an identification timing at which a clock pulse has the smallest error rate, and an output of a timing extraction filter connected at a subsequent stage. Clock pulse width adjusting means for adjusting the duty ratio so that the maximum value is obtained.

FIG. 20 is a block diagram showing a configuration of a conventional clock extracting circuit 101 as typically shown in Japanese Patent Publication No. Hei 8-4261. The clock extraction circuit 101 has an input terminal 103 for inputting pulsed input data Sin,
An output terminal 105 for outputting a clock pulse Sout; a change point differentiating circuit 110, a monostable multivibrator (hereinafter, referred to as "mono multi") 120, a falling change point differentiation The circuit 130 and the mono multi 140 are sequentially connected.

The above mono-multi 120 and mono-multi 14
0 has substantially the same internal configuration and function. FIG. 21 is a circuit diagram showing the circuit configuration of the mono-multis 120 and 140, and FIG. 22 is a timing chart for explaining the operation thereof. It is.

The mono-multis 120 and 140 are connected to an input terminal 121 to which trigger pulses S ₁₁₀ and S ₁₃₀ are input, an output terminal 122 to output an output signal S ₁₂₀ or a clock pulse Sout, and variable resistors 107 and 109. Terminal 123 to be used.

Between the power supply voltage Vcc and the terminal 123, there is provided a capacitor 124 and a constant current source 125 for outputting a constant current Io.
Are connected in series, and a connection point N between the capacitor 124 and the constant current source 125 is connected to a charging / discharging transistor 1.
26 and the (-) side input terminal of the voltage comparator 127 are connected. On the other hand, the (+) side input terminal of the voltage comparator 127 is connected to a constant current source 128 that outputs a constant current Ic, and is connected to an output terminal of the voltage comparator 127 via a resistor 129. Further, the voltage comparator 127
Is connected to a reset terminal R of a reset / set-type flip-flop (hereinafter, referred to as “RS · FF”) 141. The output terminal Q of the RS FF 141 is connected to the output terminal 122, and the inverted output terminal QN is connected to the base of the transistor 126.

[0008] The mono-multi 1 constructed as described above
20 and 140, as shown in FIG.
The FF 141 receives the set signal S supplied to the set terminal S.
s, the output signal Sq is output from the output terminal Q to the output terminal 122, and its inverted signal Sq
The transistor 126 is turned off by n. Then, when the transistor is turned off, the voltage Vin decreases, and when it falls below the reference voltage Vth,
The voltage comparator 127 outputs a reset signal Sr having a pulse width tr, and resets the RS FF 141 through the reset terminal R.

Next, the operation of the clock extraction circuit 101 configured as described above will be described with reference to FIG.
First, the changing point differentiating circuit 110 determines the pulse width Δt for each rising and falling change point of the input data Sin.
_It outputs ₁₁₀ trigger pulses _S110 .

Next, the mono multi 120 outputs a pulse signal S ₁₂₀ in synchronization with the trigger pulse S ₁₁₀ .
The pulse width t ₁₂₀ of the pulse signal S ₁₂₀ is adjustable by a variable resistor 107 connected to the power supply voltage Vee.

The falling change point differentiating circuit 130
Is a pulse signal S ₁₂₀ output from the mono multi _120.
Outputs a trigger pulse S ₁₃₀ of the pulse width Delta] t ₁₃₀ for each falling change point of.

Further, the mono-multi 140 receives the trigger pulse S ₁₃₀ output from the falling transition point differentiating circuit _130.
In synchronization with the clock pulse Sout. In addition,
The pulse width tw of the clock pulse Sout can be adjusted by the variable resistor 109 connected to the power supply voltage Vee.

Therefore, the clock extraction circuit 101
Phase delay time tp of the clock pulse Sout extracted by is consistent with the pulse width t ₁₂₀ of the pulse signal S _120, which is adjustable by the monostable multivibrator 120. Also, the pulse width tw of the clock pulse Sout can be adjusted by the mono multi 140.

[0014]

Meanwhile [0008] If an attempt is made to set the pulse width t ₁₂₀ of the pulse signal S ₁₂₀ generated by the multivibrator 120 over the period T of the input data Sin, the monostable multivibrator 120, the following Trigger pulse S
₁₁₀ is input, and the pulse signal _S120 is always on. Thus, the next stage in and arranged to have the falling change point differentiating circuit 130 of the multivibrator 120 will not be able to generate a trigger pulse S _130, consequently,
The clock extraction circuit 101 outputs the clock pulse Sout
Cannot be output. Thus, the pulse width t ₁₂₀ of the pulse signal S ₁₂₀ must be set smaller than the period T of the input data Sin. That is, the phase delay time tp of the clock pulse Sout is equal to the input data Si.
When the frequency of the input data Sin cannot be adjusted to be longer than the cycle T of n, the adjustment range of the phase delay time tp is further restricted, and in some cases, it is suitable for an identification reproduction circuit (not shown). Clock pulse S at identification timing
Out could not be given.

Accordingly, the present invention has been made in view of the above-mentioned problems of the conventional clock extracting circuit, and a first object of the present invention is to provide a clock extracting circuit having a wide range of phase adjustment of a clock pulse to be extracted. In particular, it is an object of the present invention to provide a new and improved clock extraction circuit that can handle high-frequency input data.

By the way, as shown in FIGS. 21 and 22, the mono-multi
At 0 and 140, the output signal Sq is RS · FF1
41, a set signal Ss and a reset signal S
r.

However, usually, the simultaneous ON of the set input and the reset input in the reset / set type flip-flop is often prohibited. Therefore, in the mono-multis 120 and 140, the input is input to the set terminal S of the RS / FF 141. While the set signal Ss is ON, the reset signal Sr input to the reset terminal R is turned off.
As a result, the pulse width tq of the output signal Sq could not be made narrower than the pulse width ts of the set signal Ss.

In addition, even if the pulse width ts of the set signal Ss is made extremely narrow in order to make the pulse width tq of the output signal Sq narrow, the pulse width tq will be
0, 140 could not be shorter than the operation delay time.

Here, as the frequency of the input data Sin increases, it becomes necessary to reduce the phase delay time tp and the pulse width tw of the clock pulse Sout. However, for the reasons described above, the mono multi 120,
There is a limit to shortening the pulse width tq of the output signal Sq at 140, and therefore,
In the conventional clock extraction circuit 101 having the above, it is sometimes difficult to extract the clock pulse Sout having a small phase delay time tp and / or a small pulse width tw.

Further, since the voltage comparators 127 of the mono-multis 120 and 140 usually have a high gain, the reset signal Sr output from the voltage comparator 127 is used.
It is difficult to narrow the pulse width tr of. here,
Input data Sin input to the clock extraction circuit 101
As the frequency of the signal increases, the mono multi
The frequency of the set signal Ss input to 20, 20 and 140 also increases, and the interval trs between the reset signal Sr and the set signal Ss gradually decreases. When the interval trs becomes extremely narrow or disappears, the mono-multi 12
0 and 140 cannot output a normal output signal Sq, and as a result, the clock extraction circuit 101 having these monomultis 120 and 140 cannot extract a predetermined clock pulse.

Accordingly, the present invention has been made in view of the above-mentioned problems of the conventional clock extracting circuit, and has a second object to reduce the phase delay time and pulse width of the extracted clock pulse. Provided is a new and improved clock extraction circuit that can be set extremely small and can stably extract a predetermined clock pulse even when the frequency of input data is high. It is to be.

Further, when the input data Sin whose duty ratio is deteriorated (T ₁ 1T ₂ ) is input to the clock extraction circuit 101 shown in FIG. 20, as shown in FIG. In the pulse Sout, 1
A phase shift occurs every other pulse. Due to this phase shift, the amplitude spectrum of the timing component of the clock pulse Sout deteriorates, and the clock extraction circuit 101
The output of a timing extraction filter (not shown) connected to the subsequent stage is reduced, and in some cases, clock loss or clock jitter may occur.

Therefore, the present invention has been made in view of the above-mentioned problems of the conventional clock extraction circuit, and has a third object to generate a stable clock from input data having a deteriorated duty ratio. It is to provide a new and improved clock extraction circuit that can be extracted.

[0024]

According to a first aspect of the present invention, a rising edge of pulse-like input data is differentiated according to a first aspect of the present invention. A first differentiating circuit for outputting a first trigger pulse;
A second differentiating circuit connected in parallel to the first differentiating circuit for differentiating a falling edge of the input data and outputting a second trigger pulse; and a second differentiating circuit connected in series to the first differentiating circuit. A variable pulse width first monostable multivibrator that is triggered by the first trigger pulse and outputs a first pulse signal having a predetermined pulse width;
A pulse width variable second monostable multivibrator connected in series to the second differentiator circuit and triggered by the second trigger pulse to output a second pulse signal having a predetermined pulse width; A third monostable multivibrator connected in series with the first monostable multivibrator for differentiating a falling edge of the first pulse signal and outputting a third trigger pulse; and a second monostable multivibrator. A fourth differentiating circuit connected in series to differentiate the falling edge of the second pulse signal to output a fourth trigger pulse; and a fourth differentiating circuit for the third trigger pulse and the fourth trigger pulse. A clock extraction circuit comprising: an OR gate that takes a logical sum and outputs the result as a clock pulse. According to such a configuration, since the phase adjustment range of the clock pulse can be extended, for example, twice as much as the conventional one, a stable clock pulse can be extracted without being affected by the frequency of the input data. Thus, for example, a clock pulse can be given at a suitable identification timing to the identification reproduction circuit.

Further, as set forth in claim 2, a clock pulse width adjusting means may be added to the last stage of the clock extracting circuit of claim 1. According to such a configuration, it is possible to easily change the pulse width of the extracted clock pulse. Therefore, for example, it is possible to adjust the output of the filter connected to the subsequent stage of the clock extraction circuit so as to always be the maximum.

If the clock pulse width adjusting means is a third monostable multivibrator, the pulse width of the clock pulse can be adjusted in a wide range.

Further, if the clock pulse width adjusting means is constituted by a reset / set-type flip-flop and a delay circuit, it is possible to suppress an increase in the circuit scale of the clock extraction circuit. , The pulse width of the clock pulse can be easily adjusted.

Alternatively, the clock pulse width adjusting means may be a fifth differentiating circuit. According to such a configuration, a clock extraction circuit capable of adjusting the pulse width of the extracted clock pulse is provided.
It can be realized with a smaller circuit.

According to a second aspect of the present invention, in order to solve the above-mentioned problem, a rising edge and a falling edge of pulse-like input data are differentiated, A first differentiating circuit that outputs a first trigger pulse; and a first differential circuit that is connected in series to the first differentiating circuit and outputs a first pulse signal having a predetermined pulse width triggered by the first trigger pulse. Variable pulse width first
And the first pulse signal from the first monostable multivibrator and the first pulse signal from the first differentiator are disposed after the first monostable multivibrator. And a first selection circuit that selects one of the trigger pulses and outputs the selected selection pulse as a first selection signal, and a first selection circuit connected in series with the first selection circuit to differentiate a falling edge of the first selection signal. A second differentiating circuit for outputting a second trigger pulse; and a second pulse signal having a predetermined pulse width triggered by the second trigger pulse and connected in series to the second differentiating circuit. Variable pulse width second
And the second pulse signal from the second monostable multivibrator, and the second pulse signal from the second differentiator circuit. And a second selection circuit that selects one of the trigger pulses and outputs the selected clock pulse as a clock pulse. According to this configuration, since the phase delay time and / or pulse width of the extracted clock pulse can be set small, a stable clock pulse can be extracted even when the input data frequency is high. .

Further, the first and second monostable multivibrators may be constituted by a reset / set type flip-flop and reset signal output means. According to such a configuration,
It is possible to easily adjust the phase delay time and pulse width of the extracted clock pulse.

Then, as described in claims 9 and 10,
If a differentiating circuit is provided inside the first and second monostable multivibrators, a clock pulse can be extracted from input data having a particularly high frequency. in addition,
If a delay circuit is provided inside the first and second monostable multivibrators, a clock pulse can be extracted with more stable timing.

Further, according to a third aspect of the present invention, to solve the above-mentioned problem, the present invention provides
A first differentiating circuit for differentiating a rising edge of the pulse-like input data and outputting a first trigger pulse; and a first differential circuit connected in series to the first differentiating circuit and triggered by the first trigger pulse. A pulse width variable first monostable multivibrator for outputting a first pulse signal having a predetermined pulse width, and a serially connected to the first monostable multivibrator; a rising edge of the first pulse signal; A second differentiating circuit for differentiating the falling edge and outputting a second trigger pulse; and a second differentiating circuit connected in series to the second differentiating circuit, and having a predetermined pulse width triggered by the second trigger pulse. A second monostable multivibrator that outputs a second pulse signal and has a variable pulse width; And a third differentiating circuit for differentiating the falling edge of the second pulse signal and outputting a third trigger pulse; and a third differential circuit connected in series to the third differentiating circuit, There is provided a clock extraction circuit, comprising: a pulse width variable third monostable multivibrator that outputs a clock pulse having a predetermined pulse width triggered by a trigger pulse.
According to such a configuration, it is possible to extract a clock pulse from input data having a deteriorated duty ratio at a stable timing.

According to the fourteenth aspect, a first differentiating circuit for differentiating a rising edge of the pulsed input data and outputting a first trigger pulse is connected in series to the first differentiating circuit. And a pulse width variable first monostable multivibrator that is triggered by the first trigger pulse and outputs a first pulse signal having a predetermined pulse width; and a first monostable multivibrator arranged downstream of the first monostable multivibrator. A second differentiating circuit for differentiating a rising edge of the first pulse signal and outputting a second trigger pulse; and a second differentiating circuit connected in parallel to the second differentiating circuit. Differentiating the falling edge, the third
A third differentiating circuit for outputting a trigger pulse of
A second monostable multivibrator having a variable pulse width, which is connected in series to a differentiating circuit for outputting a second pulse signal having a predetermined pulse width when triggered by the second trigger pulse; A pulse width variable third monostable multivibrator, which is connected in series to a circuit and is triggered by the third trigger pulse and outputs a third pulse signal having a predetermined pulse width; and the second monostable multivibrator. A fourth differentiating circuit connected in series with the vibrator and differentiating the falling edge of the second pulse signal to output a fourth trigger pulse;
A fifth differentiation circuit connected in series with the third monostable multivibrator for differentiating a falling edge of the third pulse signal and outputting a fifth trigger pulse; and a fourth trigger pulse. And an OR gate which takes the logical sum of the fifth trigger pulse and outputs a sixth trigger pulse, and a clock having a predetermined pulse width triggered by the sixth trigger pulse and connected in series with the OR gate. There is provided a clock extraction circuit including a pulse width variable fourth monostable multivibrator for outputting a pulse. According to such a configuration,
A clock pulse can be extracted from input data having a deteriorated duty ratio at a stable timing, and the adjustment range of the phase delay time of the extracted clock pulse is expanded.

According to the fifteenth aspect, a first differentiating circuit for differentiating the rising edge of the pulse-like input data and outputting a first trigger pulse is provided, and the first differentiating circuit is disposed at a subsequent stage of the first differentiating circuit. Triggered by the first trigger pulse, and after a predetermined delay time, a first pulse having a predetermined pulse width.
And a first monostable multivibrator that outputs a pulse signal of the first type and a second pulse signal having a predetermined pulse width triggered by the first pulse signal and arranged in series with the first monostable multivibrator. A second monostable multivibrator having a variable pulse width to be output, and a third pulse signal having a predetermined pulse width triggered by the first trigger pulse and connected in parallel to the second monostable multivibrator; A third trigger pulse which is connected in series to the third monostable multivibrator having a variable pulse width and outputs the second trigger signal by differentiating a falling edge of the second pulse signal. And a second differentiating circuit for outputting a signal in series with the third monostable multivibrator. A third differentiating circuit connected to differentiate a falling edge of the third pulse signal to output a third trigger pulse, and a logical sum of the second trigger pulse and the third trigger pulse. An OR gate for outputting a fourth trigger pulse, and a fourth pulse width variable which is connected in series to the OR gate and outputs a clock pulse having a predetermined pulse width triggered by the fourth trigger pulse. There is provided a clock extraction circuit including a monostable multivibrator. According to such a configuration, it is possible to extract a clock pulse from input data having a deteriorated duty ratio at a stable timing while suppressing the circuit scale, and to adjust the phase delay time of the extracted clock pulse. It is enlarged.

According to the sixteenth aspect, a first differentiating circuit for differentiating the rising edge of the pulsed input data and outputting a first trigger pulse is provided, and the first differentiating circuit is disposed at a subsequent stage of the first differentiating circuit. A first monostable multivibrator, which is triggered by the first trigger pulse and outputs a first pulse signal having a predetermined pulse width after a predetermined delay time, and a serial connection to the first monostable multivibrator. A second monostable multivibrator, which is triggered by the first pulse signal and outputs a second pulse signal having a predetermined pulse width after a predetermined delay time, and the second monostable multivibrator And a third pulse having a predetermined pulse width after a predetermined delay time, triggered by the first trigger pulse. A third monostable multivibrator for outputting a pulse signal, an OR gate for taking a logical sum of the second pulse signal and the third pulse signal, and outputting a fourth pulse signal, and a serial connection to the OR gate. And a pulse width variable fourth monostable multivibrator connected to the fourth pulse signal and triggered by the fourth pulse signal to output a clock pulse having a predetermined pulse width. You. According to such a configuration, it is possible to extract a clock pulse from input data having a deteriorated duty ratio at a stable timing while suppressing the circuit to a smaller scale.
The adjustment range of the phase delay time of the extracted clock pulse is also expanded.

[0036]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Some preferred embodiments of the clock extraction circuit according to the present invention will be described in detail. In the following description, components having substantially the same function and configuration will be denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) As shown in FIG. 1, a clock extraction circuit 1 according to a first embodiment of the present invention has an input terminal 2 for inputting pulse-like input data Sin.
And an output terminal 3 for outputting a clock pulse Sout. A rising change point differentiating circuit 4 and a falling change point differentiating circuit 5 are connected to the input terminal 2.
Mono-multi 6 and mono-multi 7 are connected to each. Further, a falling change point differentiating circuit 8 is connected to the monomulti 6, and a falling change point differentiating circuit 9 is connected to the monomulti 7. The output terminals of the falling point differentiating circuit 8 and the falling point differentiating circuit 9 are connected to the OR gate 1 arranged at the subsequent stage.
0 has been entered. The output terminal of the OR gate 10 is connected to a mono-multi 11, and the output terminal of the mono-multi 11 is connected to the output terminal 3.

Then, the mono-multi 6 and the mono-multi 7
Is connected to a variable resistor 12 to which a power supply voltage Vee is applied.
The variable resistor 13 to which ee is applied is connected.
The monomultis 6, 7, and 11 all have substantially the same internal configuration and function.

Next, the operation of the clock extraction circuit 1 configured as described above will be described with reference to FIG.

First, the rising change point differentiating circuit 4 generates a pulse width Δt ₄ for each rising change point of the input data Sin.
Outputs a trigger pulse S _4. Further, the falling change point differentiating circuit 5, for each falling change point of the input data Sin, and outputs a trigger pulse S ₅ of the pulse width Delta] t _5.

Next, the mono multi 6 outputs a pulse signal S ₆ in synchronization with the trigger pulse S ₄ , and the mono multi 7 outputs a pulse signal S ₇ in synchronization with the trigger pulse S _5. I do. The pulse width t of the pulse signal S ₆
Pulse width t ₇ of ₆ and S ₇ may be common adjustment by a variable resistor 12 which is connected to the power supply voltage Vee, in this clock recovery circuit 1, a pulse width t ₆
And the pulse width t ₇ are the same.

The falling transition point differentiating circuit 8 outputs a trigger pulse S ₈ having a pulse width Δt _{8 at} each falling transition point of the pulse signal S ₆ output from the mono-multi 6.
The falling transition point differentiating circuit 9 generates a pulse width Δ for each falling transition point of the pulse signal S ₇ output from the mono-multi 7.
outputs a trigger pulse S ₉ of t _9.

Then, the OR gate 10 calculates the logical sum of the trigger pulse S ₈ and the trigger pulse S ₉ and outputs the trigger pulse S ₁₀ .

Further, the mono-multi 11 is an OR gate 1
0 in synchronism with the trigger pulse S ₁₀ that is output from the output clock pulse Sout. The pulse width tw of the clock pulse Sout can be adjusted by the variable resistor 13 connected to the power supply voltage Vee.

As described above, in the clock extraction circuit 1, the phase delay time tp of the clock pulse Sout can be adjusted by the mono-multi 6 and the mono-multi 7, and the adjustment range thereof is two times the period T of the input data Sin. Less than twice. That is, the conventional clock extraction circuit 101
Approximately twice the adjustment range is secured. Therefore, the clock pulse Sout can be given to the identification reproducing circuit at a suitable identification timing without being affected by the frequency of the input data Sin. Further, the pulse width tw of the clock pulse Sout can be easily adjusted by the mono-multi 11 so that the output of a filter (not shown) connected to the subsequent stage of the clock extraction circuit 1 is maximized.

(Second Embodiment) A clock extraction circuit 16 according to a second embodiment, which includes a delay circuit 14 and an RS / FF 15 in place of the mono-multi 11 in the above-described clock extraction circuit 1, is described. May be adopted. Such a clock extraction circuit 16 according to the second embodiment.
3 is shown in FIG.

In the clock extracting circuit 16 having such a configuration, the pulse width tw of the extracted clock pulse Sout is adjusted by the delay circuit 14, and the pulse width tw of the clock pulse Sout is frequently adjusted. This is effective when there is no need to do this.

As in the second embodiment, the mono-multi 11 in the clock extracting circuit 1 is
According to the clock extraction circuit 16 having a configuration replaced with the S • FF 15, the same function as that of the clock extraction circuit 1 is realized with a smaller circuit configuration than the clock extraction circuit 1 according to the first embodiment. it can.

(Third Embodiment) Further, according to a third embodiment having a configuration in which the monomulti 11 in the clock extraction circuit 1 according to the first embodiment is replaced by a rising-change-point differentiating circuit 17. Clock extraction circuit 18
May be adopted. FIG. 4 shows the configuration of the clock extraction circuit 18 according to the third embodiment.

In the clock extraction circuit 18 having such a configuration, the pulse width tw of the clock pulse Sout to be extracted is adjusted by the rising transition point differentiating circuit 17, and therefore, the above-described second circuit is used. Similar to the clock extraction circuit 16 according to the embodiment, this is effective when it is not necessary to frequently adjust the pulse width tw of the clock pulse Sout.

Further, according to the clock extracting circuit 18 according to the third embodiment, as compared with the clock extracting circuit 16 according to the second embodiment, a predetermined clock pulse is provided with a smaller circuit configuration. It is possible to extract Sout.

In the clock extracting circuit 18 according to the third embodiment, the pulse width Δt ₈ of the trigger pulse S ₈ generated by the falling point differentiating circuit 8 and the pulse width Δt ₈ generated by the falling point differentiating circuit 9 are used. By appropriately adjusting the pulse width Δt ₉ of the triggered pulse S ₉ , the trigger pulse S ₁₀ from the OR gate ₁₀ can be directly changed to the clock pulse S 9.
It is possible to output from the output terminal 3 as out. In this case, since the rising change point differentiating circuit 17 is not required, further downsizing of the circuit can be realized.

(Fourth Embodiment) As shown in FIG. 5, a clock extraction circuit 21 according to a fourth embodiment is different from the conventional clock extraction circuit 101 described above in that it has a mono-multi 120 and a falling edge. The selection circuit 22 is additionally arranged between the point differentiating circuit 130 and the selection circuit 23 is additionally arranged between the mono multi 140 and the output terminal.

The selection circuit 22 receives a selection signal SEL ₂₂ from an input terminal 24. The selection circuit 22 receives the pulse signal S ₁₂₀ from the mono-multi 120 in response to the selection signal SEL ₂₂ . or select one of the trigger pulse S ₁₁₀ between the transition points differentiating circuit 110 as a selection signal S _22, the falling change point in the subsequent stage differentiating circuit 1
30 is output.

On the other hand, a selection signal SEL ₂₃ is input from the input terminal 25 to the selection circuit 23, and the selection circuit 23 uses the selection signal SEL _{23 to} output the pulse signal S ₁₄₀ from the monomulti ₁₄₀ or the pulse signal S _140. one of the trigger pulses S ₁₃₀ from falling change point differentiating circuit 130 is selected for the clock pulse Sout, and is configured to output to the output terminal 105.

Next, the operation of the clock extracting circuit 21 according to the fourth embodiment configured as described above will be described.
This will be described below with reference to FIG.

For example, if the selection circuit 22 is a mono-multi
Select pulse signal S ₁₂₀ from further selection circuit 2
3 by selecting a pulse signal S ₁₄₀ from the multivibrator 140, the clock extraction circuit 21 according to the fourth embodiment
Has the same function as the conventional clock extraction circuit 101.

On the other hand, the selection circuit 22 is connected to the change point differentiation circuit 11
Select trigger pulse S ₁₁₀ from 0, if further select trigger pulse S ₁₃₀ from the selection circuit 23 is falling change point differentiating circuit 130, as shown in FIG. 6, the phase delay time tp of the clock pulse Sout , Change point differentiation circuit 1
The pulse width Δt _{1 10} of the trigger pulse S ₁₁₀ generated at ₁₀
And the pulse width tw of the clock pulse Sout is
This coincides with the pulse width Δt ₁₃₀ of the trigger pulse S ₁₃₀ generated by the falling transition point differentiating circuit 130.

Normally, the changing point differentiating circuit 110 and the falling changing point differentiating circuit 130 are composed of a delay gate, an EXOR gate, an AND gate, etc., and the pulse width Δ of the trigger pulses S ₁₁₀ and S ₁₃₀ generated there.
t ₁₁₀ and Δt ₁₃₀ can be adjusted very narrowly. Therefore, the clock extraction circuit 2 according to the fourth embodiment
According to FIG. 1, with respect to the conventional clock extraction circuit 101,
Since the phase delay time tp and / or the pulse width tw of the clock pulse Sout can be set small, a stable clock pulse Sout can be extracted even when the frequency of the input data Sin is high.

(Fifth Embodiment) Next, a clock extraction circuit 31 according to a fifth embodiment will be described. FIG. 7 is a block diagram showing a circuit configuration of the clock extraction circuit 31 according to the fifth embodiment.

The clock extracting circuit 31 according to the fifth embodiment differs from the clock extracting circuit 21 according to the fourth embodiment in that the mono multi 120 is replaced with a mono multi 32 and a mono multi 140 is further added. Is replaced with a mono-multi 33.

The internal circuit configurations of the mono-multi 32 and the mono-multi 33 are substantially the same.
As shown in FIG. 8, the mono-multis 120, 140 in the clock extracting circuit 21 according to the fourth embodiment described above.
On the other hand, a differentiating circuit 34 is added before the reset terminal R of the RS FF 141. With such a configuration, according to the fifth embodiment, the reset signal Sr from the output terminal of the voltage comparator 127 once becomes
The differential circuit 34 outputs a reset trigger pulse Srd having a pulse width Δt ₃₄ at each rising transition point of the reset signal Sr. The pulse width Δt ₃₄ of the reset trigger pulse Srd is as shown in FIG.
As shown in the figure, the pulse width is set to be narrower than the pulse width tr of the reset signal Sr.

Therefore, the reset trigger pulse Srd
The interval trds between the set signal Ss and the reset signal Ss
r is larger than the interval trs between the set signal Ss and the set signal Ss input to the mono multis 32 and 33.
Is the repetition pulse period Tss of the conventional monomulti 12
0,140. That is,
The clock extracting circuit 31 according to the fifth embodiment having the mono-multis 32 and 33 is configured to obtain a higher frequency input data Sin than the clock extracting circuit 21 according to the fourth embodiment. It is possible to stably extract the clock pulse Sout.

Further, in the above-described mono-multis 32 and 33, a delay circuit 35 may be provided in a stage preceding the set terminal S of the RS / FF 141 as shown in FIG. According to such a circuit configuration, the delay circuit 35 can correct the operation delay time and the temperature fluctuation characteristic of the differentiating circuit 34 provided in the preceding stage of the reset terminal R of the RS FF 141. , 33, the pulse width t of the output signal Sq
q can be further stabilized. Therefore, according to the clock extraction circuit 31 employing the mono-multis 32 and 33, a stable clock pulse Sout can always be extracted from the input data Sin having a high frequency.

The mono-multis 32 and 33 having the circuit configuration shown in FIG. 8 or 10 are applied to the clock extraction circuit 31 according to the fifth embodiment.
Instead of the mono multi 33, the conventional clock extraction circuit 10
1 may be used. Such a configuration can be applied, for example, when high-speed operation is not required for adjusting the pulse width tw of the clock pulse Sout, and contributes to downsizing of the circuit of the clock extraction circuit 31.

In the clock extraction circuit 31, the selection circuit 22 can be omitted. According to such a configuration, the stepwise variable phase region generated by switching of the selection circuit 22 can be eliminated and the phase can be continuously reduced. It is possible to adjust the delay time tp.

(Sixth Embodiment) As shown in FIG. 11, a clock extraction circuit 41 according to a sixth embodiment is connected in series in a stage preceding the change point differentiating circuit 110 in the conventional clock extraction circuit 101 described above. It has a circuit configuration in which a rising change point differentiating circuit 42 and a mono-multi 43 are additionally arranged. The mono-multi 43 is connected to the mono-multi 120, 14 in the conventional clock extraction circuit 101.
0 has substantially the same internal configuration and function.
Further, a variable resistor 44 to which the power supply voltage Vee is applied is connected to the mono multi 43.

Next, the operation of the clock extracting circuit 41 according to the sixth embodiment configured as described above will be described.
This will be described with reference to FIG.

First, the rising change point differentiating circuit 42 generates a pulse width Δt for each rising change point of the input data Sin.
₄₂ trigger pulses _S42 are output.

The mono multi 43 outputs a pulse signal S ₄₃ in synchronization with the trigger pulse S ₄₂ . Note that the pulse width t ₄₃ of the pulse signal S ₄₃ can be adjusted by the variable resistor 44 connected to the power supply voltage Vee.

The changing point differentiating circuit 110 arranged at the lower stage of the mono-multi 43 generates a trigger pulse S ₁₁₀ (not shown) having a pulse width Δt _{110 at} each rising and falling change point of the pulse signal S _43. Output.

Next, the mono multi 120 outputs a pulse signal S ₁₂₀ in synchronization with the trigger pulse S ₁₁₀ . The pulse width t ₁₂₀ of the pulse signal S _120, the power supply voltage Vee
Can be adjusted by the variable resistor 107 connected to

The falling change point differentiating circuit 130
Is a pulse signal S ₁₂₀ output from the mono multi _120.
A trigger pulse S ₁₃₀ (not shown) having a pulse width Δt ₁₃₀ is output at each falling transition point of the signal.

Further, the mono multi 140 is provided with a trigger pulse S ₁₃₀ output from the falling transition point differentiating circuit _130.
In synchronization with the clock pulse Sout. In addition,
The pulse width tw of the clock pulse Sout can be adjusted by the variable resistor 109 connected to the power supply voltage Vee.

As described above, according to the clock extracting circuit 41 according to the sixth embodiment, as shown in FIG.
Input data Sin whose duty ratio has deteriorated (T ₁ ≠ T ₂ )
Is input, the duty ratio of the input data Sin can be corrected by the mono multi 43, so that the clock pulse So at a stable timing.
ut can be extracted, and the clock extraction circuit 4
The output of a timing extraction filter (not shown) connected to the subsequent stage of 1 does not decrease, which leads to prevention of clock loss and clock jitter.

(Seventh Embodiment) Next, as shown in FIG. 13, a clock extraction circuit 51 according to a seventh embodiment comprises an input terminal 5 for inputting pulsed input data Sin.
2 and an output terminal 53 for outputting a clock pulse Sout
And To the input terminal 52, a rising change point differentiating circuit 54 and a mono-multi 55 are connected in series.

The output side of the monomulti 55 is connected to a rising change point differentiating circuit 56 and a falling change point differentiating circuit 57, to which a monomulti 58 and a monomulti 59 are connected, respectively. In addition, Mono Multi 5
A falling change point differentiating circuit 60 is connected to 8, and a falling change point differentiating circuit 61 is connected to the monomulti 59.

The output terminals of the falling point differentiating circuit 60 and the falling point differentiating circuit 61 are input to an OR gate 62 arranged at the subsequent stage. The output terminal of the OR gate 62 is connected to the mono-multi 63, and the output terminal of the mono-multi 63 is connected to the output terminal 53.

The mono multi 55 has a power supply voltage Vee
Is connected to the variable resistor 64 to which the power supply voltage Vee is applied, and the monomulti 58 and the monomulti 59 are commonly connected to the variable resistor 65 to which the power supply voltage Vee is applied.
3 is a variable resistor 66 to which the power supply voltage Vee is applied.
Is connected. In addition, mono multi 55, 58, 5
9 and 63 all have substantially the same internal configuration and function as the monomultis 120 and 140 in the conventional clock extraction circuit 101.

The operation of the clock extraction circuit 51 according to the seventh embodiment configured as described above will be described with reference to FIG.

First, the rising change point differentiating circuit 54 outputs a trigger pulse S ₅₄ having a pulse width Δt ₅₄ at each rising change point of the input data Sin.

The mono multi 55 outputs a pulse signal S ₅₅ in synchronization with the trigger pulse S ₅₄ . In addition,
The pulse width t ₅₅ of the pulse signal S ₅₅ is equal to the power supply voltage Vee.
Can be adjusted by a variable resistor 64 connected to

The rising change point differentiating circuit 56 arranged at the lower stage of the monomulti ₅₅ outputs a trigger pulse S ₅₆ having a pulse width Δt ₅₆ at each rising change point of the pulse signal S ₅₅ . Further, the falling change point differentiating circuit 57 for each fall transition points of the pulse signal S _55, and outputs a trigger pulse S ₅₇ of the pulse width Delta] t _57.

Next, the mono multi 58 outputs a pulse signal S ₅₈ in synchronization with the trigger pulse S ₅₆ , and the mono multi 59 outputs a pulse signal S ₅₉ in synchronization with the trigger pulse S _57. I do. The pulse width t ₅₉ of the pulse width t ₅₈ and S ₅₉ of the pulse signal S _58, the power supply voltage Vee
Can be common adjustment by a variable resistor 65 which is connected to, the clock extraction circuit 51, the pulse width t ₅₈ and the pulse width t ₅₉ are the same.

Then, the falling transition point differentiating circuit 60
And outputs a trigger pulse S ₆₀ of the pulse width Delta] t ₆₀ for each falling change point of the pulse signal S ₅₈ output from the monostable multivibrator 58, the falling change point differentiating circuit 61, the monostable multivibrator 59
Outputs a trigger pulse S ₆₁ of the pulse width Delta] t ₆₁ for each falling change point of the pulse signal S ₅₉ output from.

[0086] Then, OR gate 62 takes the logical sum of the trigger pulses S ₆₀ and trigger pulses S _61, and outputs a trigger pulse S _62.

Further, the mono multi 63 is an OR gate 6
In synchronism with the trigger pulse S ₆₂ that is output from the 2 outputs a clock pulse Sout. The pulse width tw of the clock pulse Sout can be adjusted by the variable resistor 66 connected to the power supply voltage Vee.

According to the clock extraction circuit 51 according to the seventh embodiment, the duty ratio is degraded (T ₁ ≠ T ₂ ), similarly to the clock extraction circuit 41 according to the sixth embodiment. Even when the input data Sin input is input, the input data Si
Since the duty ratio of n can be corrected, the clock pulse Sout can always be extracted at a stable timing, and the output of a timing extraction filter (not shown) connected to the subsequent stage of the clock extraction circuit 51 Does not decrease, leading to prevention of clock loss and clock jitter.

Further, the maximum adjustment range of the phase delay time tp of the clock pulse Sout in the clock extraction circuit 51 is approximately twice as large as that of the conventional clock extraction circuit 101. That is, the seventh
The clock extraction circuit 51 according to the embodiment can apply a clock pulse Sout to an identification reproduction circuit (not shown) at a suitable identification timing without being restricted by the frequency of the input data Sin.

(Eighth Embodiment) A clock extraction circuit 71 according to an eighth embodiment, as shown in FIG.
The clock extraction circuit 51 according to the seventh embodiment.
55, rising change point differentiating circuit 5
A mono-multi 72 is employed in place of the sixth and falling transition point differentiating circuits 57.

That is, in the clock extraction circuit 71 according to the eighth embodiment, the input terminal 52 for inputting the pulsed input data Sin and the clock pulse S
An output terminal 53 for outputting out is provided, and a rising change point differentiating circuit 54 is connected to the input terminal 52. A monomulti 72 and a monomulti 59 are connected in parallel to the output side of the rising change point differentiating circuit 54. Further, a mono-multi 58 and a falling change point differentiating circuit 60 are sequentially connected to the output side of the mono-multi 72, and a falling change point differentiating circuit 61 is connected to the output side of the mono-multi 59.

The output terminals of the falling transition point differentiating circuit 60 and the falling transition point differentiating circuit 61 are input to an OR gate 62 disposed at a subsequent stage. It is connected to the mono multi 63. Further, the output terminal of the mono-multi 63 is connected to the output terminal 53 described above.

The mono-multi 72 has a power supply voltage Vee
The variable resistor 73 to which the power supply voltage Vee is applied is commonly connected to the monomulti 58 and the monomulti 59, and the monomulti 6 is connected to the monomulti 58 and the monomulti 59.
3 is a variable resistor 66 to which the power supply voltage Vee is applied.
Is connected.

Next, the structure of the mono-multi 72 used in the eighth embodiment will be described with reference to FIG. The monomulti 72 has a configuration in which the connection destination of the output terminal 122 is changed from the output terminal Q of the RS FF 141 to the reset terminal R of the RS FF 141, as compared with the monomultis 120 and 140 in the conventional clock extraction circuit 101. Has become. For other circuit configurations and functions, the monomulti 72 and the monomulti 12
0,140 are substantially the same.

Next, the operation of the clock extraction circuit 71 according to the eighth embodiment configured as described above will be described with reference to FIG.

First, the rising transition point differentiating circuit 54 outputs a trigger pulse S ₅₄ having a pulse width Δt ₅₄ at each rising transition point of the input data Sin.

Then, the mono multi 72 outputs a trigger pulse S ₇₂ having a pulse width Δt ₇₂ after a delay time t ₇₂ from the rising transition point of the trigger pulse S ₅₄ . The delay time t ₇₂ can be adjusted by the variable resistor 73 connected to the power supply voltage Vee.

On the other hand, the mono multi 59 outputs a pulse signal S ₅₉ in synchronization with the trigger pulse S ₅₄ . Also,
Monostable multivibrator 58 outputs a pulse signal S ₅₈ in synchronization with the trigger pulse S _72. The pulse width t ₅₈ of the pulse width t ₅₉ and the pulse signal S ₅₈ of the pulse signal S ₅₉ may be common adjustment by a variable resistor 65 which is connected to the power supply voltage Vee, pulse width t ₅₉ and the pulse width t ₅₈ is the same.

Then, the falling transition point differentiating circuit 60
And outputs a trigger pulse S ₆₀ of the pulse width Delta] t ₆₀ for each falling change point of the pulse signal S ₅₈ output from the monostable multivibrator 58, the falling change point differentiating circuit 61, the monostable multivibrator 59
Outputs a trigger pulse S ₆₁ of the pulse width Delta] t ₆₁ for each falling change point of the pulse signal S ₅₉ output from.

[0100] Then, OR gate 62 takes the logical sum of the trigger pulses S ₆₀ and trigger pulses S _61, and outputs a trigger pulse S _62.

Further, the mono multi 63 is provided with an OR gate 6
In synchronism with the trigger pulse S ₆₂ that is output from the 2 outputs a clock pulse Sout. The pulse width tw of the clock pulse Sout can be adjusted by the variable resistor 66 connected to the power supply voltage Vee.

According to the clock extracting circuit 71 according to the eighth embodiment, the same effect as that of the clock extracting circuit 51 according to the seventh embodiment can be obtained, and the clock extracting circuit 51 can As a result, the circuit is downsized, and the power consumption is reduced.

(Ninth Embodiment) A clock extraction circuit 81 according to a ninth embodiment includes, as shown in FIG.
The clock extraction circuit 71 according to the eighth embodiment.
A monomulti 83 is used in place of the monomulti 58 and the falling change point differentiating circuit 60 in FIG.
In addition, a mono multi 84 is employed in place of the falling point differentiating circuit 61.

That is, the clock extraction circuit 81 has an input terminal 52 for inputting pulsed input data Sin and an output terminal 53 for outputting a clock pulse Sout. Circuit 5
4 are connected. This rising change point differentiating circuit 54
The mono multi 72 and the mono multi 84 are connected in parallel to the output side. Further, a monomulti 83 is connected to the output side of the monomulti 72. And mono multi 8
3. Each output terminal of the mono-multi 84 is input to the OR gate 62 arranged at the subsequent stage. Also,
The output terminal of the OR gate 62 is connected to the mono-multi 63, and the output terminal of the mono-multi 63 is connected to the output terminal 53.

The power supply voltage Ve is applied to the mono multi 72.
The variable resistor 73 to which e is applied is connected, and the variable resistor 85 to which the power supply voltage Vee is applied is commonly connected to the mono-multi 83 and the mono-multi 84.

The monomultis 83 and 84 have substantially the same internal configuration and functions as the monomulti 72 shown in FIG.

Next, the operation of the clock extracting circuit 81 according to the ninth embodiment configured as described above will be described.
This will be described with reference to FIG.

First, the rising change point differentiating circuit 54 generates a pulse width Δt for each rising change point of the input data Sin.
_{The 54th} trigger pulse _S54 is output.

The mono multi 72 outputs a trigger pulse S ₇₂ having a pulse width Δt ₇₂ after a delay time t ₇₂ from the rising transition point of the trigger pulse S ₅₄ . The delay time t ₇₂ can be adjusted by the variable resistor 73 connected to the power supply voltage Vee.

On the other hand, the mono multi 84 outputs a trigger pulse S ₈₄ having a pulse width Δt ₈₄ after a delay time t ₈₄ from the rising transition point of the trigger pulse S ₅₄ . Further, the mono multi 83 outputs a trigger pulse S ₈₃ having a pulse width Δt ₈₃ after a delay time t ₈₃ from the rising change point of the trigger pulse S ₇₂ . The delay time t ₈₄ and the delay time t ₈₃ are the same as those of the variable resistor 85 connected to the power supply voltage Vee.
, The delay time t ₈₄ and the delay time t ₈₃ become the same.

[0111] Then, OR gate 62 takes the logical sum of the trigger pulse S ₈₃ and trigger pulses S _84, and outputs a trigger pulse S _62.

Further, the mono-multi 63 is the OR gate 6
In synchronism with the trigger pulse S ₆₂ that is output from the 2 outputs a clock pulse Sout. The pulse width tw of the clock pulse Sout can be adjusted by the variable resistor 66 connected to the power supply voltage Vee.

According to the clock extracting circuit 81 according to the ninth embodiment, the same effects as those of the clock extracting circuits 51 and 71 according to the seventh and eighth embodiments can be obtained. The circuit size is reduced, and power consumption is reduced.

Although the mono-multis 140 and 63 are arranged at the last stage of the clock extracting circuits 41, 51, 71 and 81 according to the sixth to ninth embodiments, the pulse width tw of the clock pulse Sout is set. If it is not necessary to frequently change, the mono-multis 140 and 63 can be omitted.

As described above, the preferred embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, in the above-described embodiment, the clock extracting circuit according to the present invention has been described by taking the clock extracting circuit in the optical receiver as an example. However, the present invention is not limited to this, and may be, for example, a PCM transmission. It is also applicable to electrical signal receivers in the system.

[0117]

According to the first to fifth aspects of the present invention, clock pulses can be extracted at predetermined timing from input data of various frequencies.

According to the second aspect of the present invention, the pulse width of the output clock pulse can be easily adjusted.

In particular, according to the third aspect of the invention, it is possible to adjust the pulse width of the clock pulse in a wide range.

According to the present invention, the pulse width of the clock pulse can be adjusted while suppressing an increase in the circuit scale of the clock extraction circuit.

According to the present invention, it is possible to extract a clock pulse from input data having a particularly high frequency.

In particular, according to the ninth and tenth aspects of the present invention, it is possible to cope with input data having a higher frequency.
According to the eleventh and twelfth aspects, a more stable clock pulse can be extracted.

According to the thirteenth to sixteenth aspects,
Even when the duty ratio of the input data is deteriorated, a stable clock pulse can be extracted.

In particular, according to the present invention, the adjustment range of the phase delay time of the extracted clock pulse can be expanded.

Further, according to the present invention, a small-scale circuit configuration can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the clock extraction circuit of FIG. 1;

FIG. 3 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a fourth embodiment of the present invention.

FIG. 6 is a timing chart illustrating an operation of the clock extraction circuit of FIG. 5;

FIG. 7 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a fifth embodiment of the present invention.

8 is a circuit diagram showing a circuit configuration inside a mono-multi used in the clock extraction circuit of FIG. 7;

FIG. 9 is a timing chart showing the operation of the mono-multi in FIG. 8;

FIG. 10 is a circuit diagram showing an internal circuit configuration of another mono-multi which can be used for the clock extraction circuit of FIG. 7;

FIG. 11 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a sixth embodiment of the present invention.

FIG. 12 is a timing chart illustrating an operation of the clock extraction circuit of FIG. 11;

FIG. 13 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a seventh embodiment of the present invention.

FIG. 14 is a timing chart illustrating the operation of the clock extraction circuit of FIG. 13;

FIG. 15 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to an eighth embodiment of the present invention.

16 is a circuit diagram showing a circuit configuration inside a mono-multi used in the clock extraction circuit of FIG.

FIG. 17 is a timing chart showing an operation of the clock extraction circuit of FIG. 15;

FIG. 18 is a block diagram illustrating a schematic configuration of a clock extraction circuit according to a ninth embodiment of the present invention.

FIG. 19 is a timing chart showing the operation of the clock extraction circuit of FIG. 18;

FIG. 20 is a block diagram showing a schematic configuration of a conventional clock extraction circuit.

21 is a circuit diagram showing a circuit configuration inside a mono-multi used in the clock extraction circuit of FIG. 20;

FIG. 22 is a timing chart showing the operation of the mono-multi in FIG. 21.

FIG. 23 is a timing chart showing the operation of the clock extraction circuit of FIG. 20;

FIG. 24 is a timing chart showing another operation of the clock extraction circuit of FIG. 20;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Clock extraction circuit 4 Rise change point differentiation circuit 5, 8, 9 Falling change point differentiation circuit 6, 7, 11 Mono multi 10 OR gate 14 Delay circuit 15 RS / FF 22, 23 Selection circuit 34 Differentiation circuit 35 Delay circuit 110 Change point differentiation circuit 141 RS / FF

Claims (16)

[Claims] A first differentiating circuit for differentiating a rising edge of the pulsed input data and outputting a first trigger pulse; a first differentiating circuit connected in parallel to the first differentiating circuit, A second differentiating circuit for differentiating a falling edge and outputting a second trigger pulse; a second differentiating circuit connected in series to the first differentiating circuit and having a predetermined pulse width triggered by the first trigger pulse. A first monostable multivibrator having a variable pulse width for outputting one pulse signal; a second monostable multivibrator connected in series to the second differentiating circuit and having a predetermined pulse width triggered by the second trigger pulse; A variable pulse width second monostable multivibrator for outputting a pulse signal; connected in series to the first monostable multivibrator; A third differentiating circuit for differentiating the falling edge and outputting a third trigger pulse; connected in series to the second monostable multivibrator, for differentiating the falling edge of the second pulse signal , 4th
A fourth differentiating circuit for outputting a trigger pulse of
And an OR gate for taking a logical sum of the trigger pulse and the fourth trigger pulse and outputting the result as a clock pulse. 2. A first differentiating circuit for differentiating a rising edge of the pulsed input data and outputting a first trigger pulse; and a first differentiating circuit connected in parallel to the first differentiating circuit to rise the input data. A second differentiating circuit for differentiating a falling edge and outputting a second trigger pulse; a second differentiating circuit connected in series to the first differentiating circuit and having a predetermined pulse width triggered by the first trigger pulse. A first monostable multivibrator having a variable pulse width for outputting one pulse signal; a second monostable multivibrator connected in series to the second differentiating circuit and having a predetermined pulse width triggered by the second trigger pulse; A variable pulse width second monostable multivibrator for outputting a pulse signal; connected in series to the first monostable multivibrator; A third differentiating circuit for differentiating the falling edge and outputting a third trigger pulse; connected in series to the second monostable multivibrator, for differentiating the falling edge of the second pulse signal , 4th
A fourth differentiating circuit for outputting a trigger pulse of
An OR gate which takes the logical sum of the above trigger pulse and the fourth trigger pulse and outputs a fifth trigger pulse; a predetermined pulse which is connected in series to the OR gate and is triggered by the fifth trigger pulse And a clock pulse width adjusting means for outputting a clock pulse having a width. 3. The clock pulse width adjusting means is a pulse width variable third monostable multivibrator which is triggered by the fifth trigger pulse and outputs a clock pulse having a predetermined pulse width. 3. The clock extraction circuit according to claim 2, wherein 4. The clock pulse width adjusting means includes a reset-set flip-flop that outputs a clock pulse set by the fifth trigger pulse, and a delay that delays the fifth trigger pulse by a predetermined time. 3. The clock extraction device according to claim 2, comprising a delay circuit that outputs a signal, wherein the reset-set flip-flop is configured to be reset by the delay signal from the delay circuit. circuit. 5. The clock pulse width adjusting means is a fifth differentiation circuit that differentiates a rising edge of the fifth trigger pulse and outputs a clock pulse having a predetermined pulse width. A clock extraction circuit according to claim 2. 6. A first differentiating circuit for differentiating a rising edge and a falling edge of pulse-like input data and outputting a first trigger pulse; and a first differentiating circuit connected in series to said first differentiating circuit; A variable pulse width first monostable multivibrator that is triggered by a first trigger pulse and outputs a first pulse signal with a predetermined pulse width; A first which selects one of the first pulse signal from the first monostable multivibrator and the first trigger pulse from the first differentiating circuit and outputs the selected signal as a first selection signal A selection circuit;
A second differentiation circuit connected in series with the first selection circuit and differentiating a falling edge of the first selection signal to output a second trigger pulse; and a second differentiation circuit connected in series with the second differentiation circuit. A second monostable multivibrator having a variable pulse width, the second monostable multivibrator being connected to the second trigger pulse and outputting a second pulse signal having a predetermined pulse width when triggered by the second trigger pulse; And selects one of the second pulse signal from the second monostable multivibrator and the second trigger pulse from the second differentiating circuit and outputs the selected signal as a clock pulse. Two selection circuits;
A clock extraction circuit comprising: 7. A reset-set flip-flop that is set by the first trigger pulse and outputs the first pulse signal, wherein the first monostable multivibrator includes: a reset-set flip-flop that outputs the first pulse signal; 7. A clock extraction circuit according to claim 6, further comprising: reset signal output means for supplying a reset signal at a predetermined timing. 8. The reset-set flip-flop, wherein the second monostable multivibrator is set by the second trigger pulse and outputs the second pulse signal; 8. The clock extracting circuit according to claim 6, further comprising: reset signal output means for supplying a reset signal at a predetermined timing. 9. The first monostable multivibrator, wherein the reset signal is configured to be input to the reset / set-type flip-flop via a differentiating circuit. Clock extraction circuit according to 7. 10. The second monostable multivibrator, wherein the reset signal is configured to be input to the reset / set-type flip-flop via a differentiating circuit. Clock extraction circuit according to claim 8 11. The first monostable multivibrator is characterized in that the first trigger pulse is inputted to the reset / set-type flip-flop via a delay circuit. 10. A clock extraction circuit according to claim 9, 12. The second monostable multivibrator is characterized in that the second trigger pulse is input to the reset / set-type flip-flop via a delay circuit. 11. A clock extraction circuit according to claim 10. 13. A first differentiating circuit for differentiating a rising edge of pulse-like input data and outputting a first trigger pulse; and a first triggering circuit connected in series to said first differentiating circuit, A pulse width variable first monostable multivibrator that is triggered by a pulse and outputs a first pulse signal having a predetermined pulse width; and the first pulse is connected in series to the first monostable multivibrator and is connected to the first monostable multivibrator. A second differentiating circuit for differentiating a rising edge and a falling edge of the signal to output a second trigger pulse; connected in series to the second differentiating circuit and triggered by the second trigger pulse A variable pulse width second monostable multivibrator for outputting a second pulse signal having a predetermined pulse width; and the second monostable multivibrator. A third differentiating circuit connected in series with the ibrator to differentiate a falling edge of the second pulse signal and output a third trigger pulse; and a third differentiating circuit connected in series to the third differentiating circuit; A pulse width variable third monostable multivibrator that is triggered by the third trigger pulse and outputs a clock pulse having a predetermined pulse width. 14. A first differentiating circuit for differentiating a rising edge of pulse-like input data and outputting a first trigger pulse; and a first trigger circuit connected in series to said first differentiating circuit, A variable pulse width first monostable multivibrator that is triggered by a pulse and outputs a first pulse signal having a predetermined pulse width; and a first pulse arranged at a stage subsequent to the first monostable multivibrator, A second differentiating circuit for differentiating a rising edge of the signal and outputting a second trigger pulse; connected in parallel to the second differentiating circuit, for differentiating a falling edge of the first pulse signal A third differentiating circuit for outputting a third trigger pulse; a second differentiating circuit connected in series to the second differentiating circuit and having a predetermined pulse width triggered by the second trigger pulse; A variable pulse width second monostable multivibrator that outputs a pulse signal of a third pulse; a third pulse having a predetermined pulse width triggered by the third trigger pulse and serially connected to the third differentiating circuit; A variable pulse width third monostable multivibrator for outputting a signal; a fourth trigger connected in series with the second monostable multivibrator to differentiate a falling edge of the second pulse signal; A fourth differentiating circuit for outputting a pulse; and a fifth differential circuit connected in series to the third monostable multivibrator for differentiating a falling edge of the third pulse signal to output a fifth trigger pulse. And an OR gate for calculating a logical sum of the fourth trigger pulse and the fifth trigger pulse and outputting a sixth trigger pulse; A variable pulse width fourth monostable multivibrator, which is connected in series to the OR gate and outputs a clock pulse having a predetermined pulse width triggered by the sixth trigger pulse. Clock extraction circuit. 15. A first differentiating circuit for differentiating a rising edge of pulse-like input data to output a first trigger pulse; and a first trigger circuit disposed at a stage subsequent to the first differentiating circuit, the first trigger circuit comprising: A first monostable multivibrator that is triggered by a pulse and outputs a first pulse signal having a predetermined pulse width after a predetermined delay time;
A second monostable multivibrator having a variable pulse width, which is arranged in series with the monostable multivibrator and outputs a second pulse signal having a predetermined pulse width triggered by the first pulse signal;
A variable pulse-width third monostable multivibrator connected in parallel to the monostable multivibrator of the present invention and triggered by the first trigger pulse to output a third pulse signal of a predetermined pulse width; A second differentiating circuit connected in series to the second monostable multivibrator and differentiating a falling edge of the second pulse signal to output a second trigger pulse;
A third differentiation circuit connected in series with the third monostable multivibrator to differentiate a falling edge of the third pulse signal and output a third trigger pulse; the second trigger pulse An OR gate for calculating a logical sum of the third trigger pulse and the fourth trigger pulse and outputting a fourth trigger pulse; a clock having a predetermined pulse width triggered by the fourth trigger pulse and serially connected to the OR gate; A fourth pulse monostable multivibrator that outputs a pulse and has a variable pulse width. 16. A first differentiator circuit for differentiating a rising edge of pulse-like input data and outputting a first trigger pulse; and a first trigger circuit arranged at a stage subsequent to the first differentiator circuit, A first monostable multivibrator that is triggered by a pulse and outputs a first pulse signal having a predetermined pulse width after a predetermined delay time;
A second monostable multivibrator, which is arranged in series with the monostable multivibrator and outputs a second pulse signal having a predetermined pulse width after a predetermined delay time, triggered by the first pulse signal; A third monostable multivibrator connected in parallel to the second monostable multivibrator and triggered by the first trigger pulse to output a third pulse signal having a predetermined pulse width after a predetermined delay time; An OR gate for taking the logical sum of the second pulse signal and the third pulse signal and outputting a fourth pulse signal; and an OR gate connected in series to the OR gate, triggered by the fourth pulse signal A variable pulse width monostable multivibrator for outputting a clock pulse having a predetermined pulse width Clock extraction circuit comprising the.